Silicon Design Verification Engineer, FPGA/System Verilog

Amd

Quick summary

Work type
On-site
Location
San Jose, CA
Posted
110 days ago
Closes
Mar 9, 2027
Nearby
99+ roles within 25 mi

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Similar $187k
$133k most similar roles pay here $233k

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About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

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TL;DR · Silicon Design Verification Engineer, FPGA/System Verilog

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As a senior verification engineer on AMD’s FPGA team, you will lead the functional correctness and quality assurance of new and existing features for advanced processor devices. Your daily tasks include collaborating with architects and hardware engineers to develop comprehensive test plans, estimating test development time, building directed and random verification tests, debugging failures, and ensuring coverage metrics meet requirements. Ideal candidates have strong experience in UVM-based verification environments, proficiency in SystemVerilog, Verilog, C, and C++, scripting skills with Python, and a solid understanding of UVM concepts and SystemC. This role involves working on large-scale digital subsystems to deliver robust designs for complex business problems in the semiconductor industry.

Skills

SystemVerilog UVM Python C++ Verilog SystemC TLM Simulation tools Distributed compute environment HLS tools CI/CD

What you'll do

  • Develop comprehensive verification strategies for AMD’s FPGA devices.
  • Create detailed test plans considering interactions with other features and environments.
  • Estimate time requirements for writing new feature tests and modifying test environments.
  • Build directed and random verification tests to ensure functional correctness.
  • Debug test failures to identify root causes and resolve design defects collaboratively.

What we're looking for

  • Strong analytical and debugging skills for complex digital subsystems.
  • Experience developing UVM-based verification environments and testbenches.
  • Proficiency in SystemVerilog, Verilog, C, and C++.
  • Scripting experience with Python or similar automation languages.
  • Good understanding of UVM concepts and SystemVerilog language.

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