Signal Integrity Engineer, Memory Interface

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Austin, TX
Posted: 15 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $201k

$140k most similar roles pay here $243k

This listing doesn't post a salary. Most similar roles pay $168,500–$233,050.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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TL;DR · Signal Integrity Engineer, Memory Interface

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As a Signal Integrity Engineer – Memory Interface, you will join the team developing SoCs for mobile devices. You are responsible for memory interface signal integrity from package to board, focusing on electrical and physical design of memory systems. Your daily work involves performing end-to-end signal and power integrity simulation studies, modeling channels and power delivery networks across die, interposer, package, PCB, and PMU components to meet strict timing and voltage specifications. You will collaborate with circuit and controller teams to optimize designs, provide feedback on silicon floorplans, and perform feasibility studies for next-generation signaling schemes. Required expertise includes DDR or LPDDR interfaces, transmission line theory, and 2D/3D EM simulation tools. You will utilize Python and lab equipment like VNA, TDR, and real-time scopes to validate results and improve product yield through correlation between simulation and silicon measurement.

Skills

Signal Integrity Power Integrity DDR LPDDR EM Simulation Transmission Line Theory Python VNA TDR Real-time Scope Spectrum Analyzer Validation

What you'll do

Perform end-to-end signal and power integrity simulation studies for memory systems from die to PCB.
Model channels and power delivery networks to meet strict timing and voltage specifications.
Conduct electrical extraction and validation of package and motherboard designs.
Develop and execute test plans to validate signal and power integrity.
Provide design guidelines and optimal IO settings to cross-functional teams.
Perform feasibility studies for next-generation signaling schemes.
Correlate simulation results with actual silicon measurements.
Debug and improve product yield in collaboration with product and system engineering teams.

What we're looking for

BS degree and 10 years of industry experience.
MSEE or Ph.D. with 8 years of experience (preferred).
Prior design and modeling experience with DDR or LPDDR interfaces.
Experience with signal and power integrity issues of memory interfaces (preferred).
Experience with package/board design, PI/SI methodology development, and lab correlation (preferred).
Familiarity with lab equipment such as VNA, TDR, real-time scope, and spectrum analyzers (preferred).
Strong fundamentals in 3D/2D EM simulation tools and transmission line theory (preferred).
Proficiency in Python and experience using generative AI coding assistants (preferred).