Signal Integrity Engineer, Memory Interface

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$184,700–$324,800 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $201k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 95% of similar roles. Most pay $168,500–$233,050 — the shaded band above. At the midpoint, this role pays about $255k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · Signal Integrity Engineer, Memory Interface

As a Signal Integrity Engineer – Memory Interface, you will join the team developing SoCs for mobile devices. You are responsible for memory interface signal integrity from package to board, specifically focusing on DDR and LPDDR interfaces. Your daily work involves the electrical and physical design of memory systems, including extraction and validation of packages and multi-layer boards. You will perform end-to-end signal and power integrity simulation studies, model channels and power delivery networks, and conduct feasibility studies for next-generation signaling schemes. To succeed, you must utilize 2D/3D EM simulation tools, transmission line theory, and Python coding with generative AI assistants. You will also use lab equipment like VNAs, TDRs, and real-time scopes to correlate simulations with silicon measurements while collaborating with cross-functional teams to optimize designs and improve product yield.

What you'll do

  • Conduct end-to-end signal and power integrity simulation studies for memory systems from die to PCB.
  • Model channels and power delivery networks to meet strict timing and voltage specifications.
  • Perform electrical extraction and validation of package and multi-layer board (MLB) designs.
  • Develop and execute test plans to validate signal and power integrity.
  • Correlate simulation results with actual silicon measurements.
  • Provide design guidelines and optimal IO settings to cross-functional teams.
  • Conduct feasibility studies for next-generation signaling schemes.
  • Debug and improve product yield in collaboration with product and system engineering teams.

What we're looking for

  • BS degree and 10 years of industry experience.
  • Prior design and modeling experience with DDR or LPDDR interfaces.
  • MSEE plus 8 years of experience or a Ph.D. (preferred).
  • Experience with signal and power integrity issues of memory interfaces (preferred).
  • Experience with package/board design, PI/SI methodology development, and lab correlation (preferred).
  • Familiarity with lab equipment such as VNA, TDR, real-time scope, and spectrum analyzers (preferred).
  • Strong fundamentals in 3D/2D EM simulation tools and transmission line theory (preferred).
  • Proficiency in Python and experience using generative AI coding assistants (preferred).

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