Signal Integrity Engineer – Memory Interface

Apple Inc

Quick summary

Work type
On-site
Location
San Francisco, CA
Salary
$126,800–$220,900 / yr
Posted
45 days ago

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $187k
This role $174k
$116k most similar roles pay here $232k

This role pays less than 67% of similar roles. Most pay $165,200–$209,750 — the shaded band above. At the midpoint, this role pays about $174k versus about $187k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 969 open roles on FindRole.

Listed pay typically runs $163,300–$272,100 across 756 roles with salary data.

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At a glance

TL;DR · Signal Integrity Engineer – Memory Interface

As a Signal Integrity Engineer at Apple’s SOC development team, you will focus on memory interface signal integrity for mobile devices, covering design from package to board. Your daily tasks include electrical and physical design of memory systems, extraction and validation of packages, collaboration with circuit and controller teams for optimization, SI and PI modeling, simulation, characterization, and test plan execution for validation. You will also work closely with product engineering and system engineering to debug and improve yield. Essential skills include experience in signal and power integrity issues, familiarity with lab equipment like VNAs and real-time scopes, proficiency in 3D/2D EM simulations, and strong Python coding abilities enhanced by AI tools. This role demands expertise in optimizing IO settings and conducting feasibility studies for new signaling schemes, ensuring tight timing and voltage specifications are met across various components of the memory system.

What you'll do

  • Conduct end-to-end signal integrity and power integrity simulations of memory systems.
  • Provide feedback and guidelines for silicon floorplan, package, system design teams.
  • Develop optimal IO settings and design guidelines for cross-functional teams.
  • Perform feasibility studies for next generation signaling schemes.
  • Correlate simulation results with actual silicon measurements.

What we're looking for

  • MSEE + 5 years of industry experience or Ph.D. in relevant field
  • Extensive experience with signal and power integrity issues in memory interfaces
  • Experience in package/board design analysis, PI/SI methodology development, and lab validation
  • Proficiency in using lab equipment like VNA, TDR, real-time scopes, spectrum analyzers
  • Strong fundamentals in 3D/2D EM simulation tools and transmission line theory
  • Expertise in Python with foundational coding skills and AI coding assistants

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