SerDes System Validation Engineer

What you'll do

• Lead the bring-up, validation, and debug of mixed-signal SerDes IP in system environments.
• Analyze robustness and margins of high-speed serial links within a system context.
• Collaborate with design teams to define DFT requirements for improved testability and first-time silicon success.
• Perform mixed-signal verification tasks to understand SerDes operation and interaction with control logic.
• Develop scripts in Python, C, or Matlab to automate validation efforts.
• Execute lab testing and define equipment needs for high-speed serial link bring-up.
• Manage the transition from pre-silicon verification through silicon debug and production ramp.
• Evaluate SerDes architecture components including CDR, equalization techniques, and link jitter budgets.

What we're looking for

• Bachelor of Science degree and at least 10 years of relevant industry experience.
• Experience with high-speed SerDes protocols such as PCIe, USB, UCIe, or OIF (preferred).
• Experience with system bring-up of high-speed serial links, lab testing, and defining equipment needs (preferred).
• Proficiency in scripting languages like Python, C, or Matlab for automation (preferred).
• Knowledge of SerDes design and architecture including CDR, equalization, and ADC based links (preferred).
• Experience in mixed-signal circuit pre-silicon verification and silicon bring-up (preferred).
• Knowledge of DFT to aid in system validation (preferred).
• Familiarity with PCB design, ESD requirements, and link jitter budgets (preferred).