Senior VLSI Library Methodology Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$136,000–$218,500 / yr
Posted
9 days ago
Freshness
Confirmed live yesterday

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k
This role $177k
$124k most similar roles pay here $249k

This role pays less than 61% of similar roles. Most pay $177,250–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $197k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior VLSI Library Methodology Engineer

As a Senior VLSI Library Methodology Engineer, you will join the team to drive the development, specification, and implementation of scalable systems supporting library analysis, quality validation, documentation, and deployment for Physical Design flows. You will architect and implement automation systems for examining, verifying, issue checking, reporting, and release readiness across GPU and SoC flows. Your daily work involves building end-to-end infrastructure including analysis pipelines, regression frameworks, and dashboards while collaborating with methodology, library, and build teams to improve quality on advanced nodes. The role requires proficiency in Python, C++, or Perl, along with experience using EDA tools such as Innovus, Fusion Compiler, Crosscheck, and Virtuoso. You will solve complex problems regarding data integrity, quality metrics, and resource efficiency while ensuring robust automation for large-scale library modeling and physical design flows.

What you'll do

  • Architect and implement scalable automation systems for examining, verifying, and reporting across GPU and SoC flows.
  • Build end-to-end infrastructure including analysis pipelines, regression frameworks, and reporting dashboards.
  • Develop automated library analysis and quality control flows using modern scripting and EDA tools.
  • Optimize large-scale analysis workflows for runtime, capacity, and resource efficiency.
  • Integrate quality systems and improve cell design methodologies in collaboration with design and CAD teams.
  • Define methodologies for issue triage, data integrity, and release criteria to improve decision-making.
  • Develop production-quality technical systems focusing on scalability and operational robustness.

What we're looking for

  • M.S. in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent experience).
  • 4+ years of experience in library methodology, physical design, CAD, design automation, or related VLSI infrastructure development.
  • Strong software development skills in Python, C++, or Perl for building workflow automation and data pipelines.
  • Experience designing and implementing production-quality technical systems with a focus on scalability and operational robustness.
  • Hands-on experience with industry-standard EDA tools such as Innovus, Fusion Compiler, Crosscheck, Virtuoso, or similar.
  • Experience developing automated library analysis, validation, and quality control flows using modern scripting and EDA tools.
  • Knowledge of how library models are consumed in chip design flows including synthesis, P&R, timing closure, and power analysis.
  • Experience building infrastructure to track metrics such as validation pass rates, regression health, and resource utilization.

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