This role pays more than
79%
of similar roles. Most pay
$167,500–$220,800
— the shaded band above.
At the midpoint, this role pays about
$225k
versus about
$194k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
As a Senior Staff/Principal Reliability Engineer within the Reliability Development Engineering team, you will lead the definition and execution of reliability strategies for advanced semiconductor technologies. You will be responsible for ensuring robust qualification and technology certification across devices, packages, and systems while managing complex SoCs and advanced packaging architectures like 2.5D/3D integration and chiplets. Your daily work involves performing advanced reliability analysis on mechanisms such as BTI, TDDB, HCI, electromigration, and self-heating to assess design and process robustness. You will utilize tools like JMP or Minitab for statistical analysis and lifetime modeling while providing expert judgment on critical trade-offs. The role requires deep expertise in semiconductor physics, advanced CMOS nodes, and translating device-level data into system-level metrics to mitigate risks across the full product lifecycle while collaborating with cross-functional teams.
Define foundry qualification requirements and execute technology certification for complex designs and advanced technologies.
Lead reliability strategy and execution for high-impact products across devices, packages, and systems.
Perform and guide advanced reliability analysis including aging, wear-out, and electromigration modeling to assess design robustness.
Identify and mitigate non-obvious reliability risks throughout the entire product lifecycle.
Establish scalable organizational reliability processes and best practices for future technology generations.
Provide expert technical judgment on critical trade-offs between performance, power, quality, and schedule.
Review and approve design waivers for electromigration violations in SoC designs and packaging interfaces.
Communicate reliability status, risks, and strategic recommendations to senior leadership and executive stakeholders.
What we're looking for
Bachelor's degree with 8+ years of experience, Master's with 7+ years, or PhD with 6+ years in a relevant engineering field.
10 to 15 years of industry experience in semiconductor reliability engineering, technology development, or product qualification for advanced CMOS nodes.
Deep expertise in device and interconnect reliability physics including BTI, TDDB, HCI, electromigration, self-heating, and wear-out mechanisms.
Hands-on experience designing reliability test structures and interpreting complex data from various reliability mechanisms.
Strong background in advanced packaging and heterogeneous integration, including TSV-based 2.5D/3D integration and chiplet architectures.
Proficiency in advanced statistical analysis and lifetime modeling using tools like Weibull analysis, JMP, or Minitab.
Proven ability to translate device-level reliability data into circuit and system-level metrics for complex digital SoCs.
Demonstrated technical leadership in mentoring engineers and influencing cross-functional design, process, and program decisions.
Remote (Irvine, CA)+115 days ago
$192,400–$275,800
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