Senior Mask Design Engineer, Hardware

Nvidia

Confirmed live 4 days ago Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $132,000–$207,000 / yr
Posted: 180 days ago
Freshness: Confirmed live 4 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $192k

This role $170k

$122k most similar roles pay here $229k

This role pays less than 74% of similar roles. Most pay $169,250–$214,000 — the shaded band above. At the midpoint, this role pays about $170k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Senior Mask Design Engineer, Hardware

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As a Senior Mask Design Engineer - Hardware, you will join a multifaceted team responsible for handling significant high-speed mixed-signal circuit designs. Your daily responsibilities involve performing physical layout for mixed-signal functions including PLLs, high-speed SerDes, Analog to Digital converters, and ESD structures in state-of-the-art sub-micron CMOS technologies. You will collaborate cross-functionally with ASIC and mixed-signal engineers to customize designs for integration into VLSI products while participating in floor planning, custom layout, and verifying against design rules and schematics. The role requires expertise in Cadence tools, specifically Virtuoso, along with experience using verification tools like Dracula, Hercules, Calibre, and Prime-yield. You must possess a deep understanding of analog circuit layout concepts and proficiency in scripting languages such as Perl, Python, and Skill to manage DRC and LVS checking flows.

Skills

Mask Layout Mixed-Signal SerDes CMOS VLSI DRC LVS Calibre Python Perl SKILL Floor Planning

What you'll do

Perform physical layout for mixed-signal functions like PLLs, high-speed SerDes, and ADC structures.
Design layouts using state-of-the-art sub-micron CMOS technologies with Cadence tools.
Collaborate with ASIC and mixed-signal engineers to customize designs for VLSI product integration.
Participate in floor planning and custom layout development.
Verify designs against specific design rules and schematics.
Run and debug layouts using verification tools like Dracula, Hercules, Calibre, and Prime-yield.
Manage DRC and LVS checking flows and customize associated decks.

What we're looking for

Bachelor of Science in Electrical Engineering (BSEE) or equivalent experience.
Proven experience in Mask and Layout Design.
Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
Expertise in Cadence custom circuit design tools, specifically Virtuoso.
Experience running and debugging with verification tools such as Dracula, Hercules, Calibre, and Prime-yield.
Proficiency in scripting languages including Perl, Python, and SKILL.
Knowledge of DRC and LVS checking flows and the ability to customize decks.

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