Senior Mask Design Engineer - Hardware

Nvidia

Remote

Quick summary

Work type: Remote
Location: Santa Clara, CA
Salary: $132,000–$207,000 / yr
Posted: 65 days ago

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Competitive pay

How this pay compares to similar roles

Similar $180k

This role $170k

$123k most similar roles pay here $220k

This role pays less than 65% of similar roles. Most pay $155,425–$205,000 — the shaded band above. At the midpoint, this role pays about $170k versus about $180k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 563 open roles on FindRole.

Listed pay typically runs $168,000–$264,500 across 556 roles with salary data.

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At a glance

TL;DR · Senior Mask Design Engineer - Hardware

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As a senior Mask Layout Design Engineer on our cutting-edge semiconductor team, you will be responsible for creating physical layouts for complex mixed-signal functions such as PLLs, high-speed SerDes, and analog-to-digital converters using state-of-the-art sub-micron CMOS technologies. Your daily tasks will involve designing ESD structures and leveraging Cadence tools to ensure the highest quality mask layout designs. Ideal candidates possess at least seven years of hands-on experience in mask and layout design, along with a deep understanding of semiconductor fabrication processes. This role demands expertise in advanced CMOS technology nodes and proficiency in using industry-standard EDA software. You will contribute to developing innovative solutions for high-performance mixed-signal ICs, addressing critical challenges in the rapidly evolving field of integrated circuit design.

Skills

Cadence CMOS PLL SerDes Analog to Digital converters ESD structures Sub-micron CMOS technologies

What you'll do

Perform physical layout for mixed-signal functions such as PLLs using Cadence tools.
Design high-speed SerDes structures in advanced sub-micron CMOS technologies.
Create layouts for analog to digital converters with precision and efficiency.
Develop ESD structures designs ensuring robustness against electrostatic discharge.
Utilize cutting-edge CMOS technologies for mask layout design tasks.