Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Samsung Semiconductor

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
46 days ago
Freshness
Confirmed live today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $200k
This role $172k
$126k $254k
below market most similar roles pay here above market

This role pays less than 71% of similar roles. Most pay $163,500–$235,750 — the blue band above. At the midpoint, this role pays about $172k versus about $200k for comparable roles.

Based on 240 similar postings.

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About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 37 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 37 roles with salary data.

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At a glance

TL;DR · Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

The Senior Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU joins the Architecture Research Lab to develop next-generation RISC-V microarchitecture. This role involves researching emerging computing workloads, evaluating performance potential, and transforming concepts into designs for silicon validation. You will drive microarchitectural research and performance modeling, analyzing workloads to identify bottlenecks across the front-end, mid-end, and back-end. Key responsibilities include running architectural simulations, developing automation scripts, and utilizing AI-driven design methodologies to accelerate exploration. Required skills include proficiency in C/C++ and Python, experience with the gem5 simulator, and a deep understanding of out-of-order execution, branch prediction, and cache systems. The work focuses on solving performance and efficiency requirements for data center and agentic AI workloads while exploring CPU-memory co-design.

What you'll do

  • Drive microarchitectural research and performance modeling for next-generation RISC-V CPU architectures.
  • Analyze emerging data center and agentic AI workloads to identify architectural opportunities.
  • Develop and refine performance models to analyze IPC, CPI stacks, latency, and throughput.
  • Identify performance bottlenecks and optimization opportunities across the front-end, mid-end, and back-end.
  • Characterize workloads and benchmarks to understand performance behavior and architectural requirements.
  • Develop scripts and tools to automate performance analysis and accelerate architectural exploration.
  • Implement promising microarchitectural concepts through RTL design and silicon validation.
  • Contribute to patents and technical publications based on novel architectural research.

What we're looking for

  • Master’s degree in Computer Architecture, Computer Engineering, or a related field.
  • 3+ years of experience or a PhD degree in Computer Architecture, Computer Engineering, or a related field.
  • 1+ years of experience in CPU microarchitecture or performance engineering.
  • Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
  • Hands-on experience with architectural simulators such as gem5.
  • Proficiency in C/C++ and Python.
  • Experience with RISC-V, ARM, or x86 CPU cores, or with GPU/NPU vector unit design (preferred).
  • Experience with AI-driven design workflows, agentic AI workloads, PPA trade-offs, or silicon validation (preferred).

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