Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

Samsung Semiconductor

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$163,000–$253,000 / yr
Posted
46 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $213k
This role $208k
$150k $280k
below market most similar roles pay here above market

This role pays less than 56% of similar roles. Most pay $179,575–$246,000 — the blue band above. At the midpoint, this role pays about $208k versus about $213k for comparable roles.

Based on 240 similar postings.

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About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 37 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 37 roles with salary data.

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At a glance

TL;DR · Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU

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The Staff Engineer, Architecture & Performance Research Engineer for Data Center and Agentic AI CPU joins the Architecture Research Lab to develop next-generation RISC-V microarchitecture. This role involves researching emerging computing workloads, evaluating performance potential, and transforming concepts into designs for silicon validation. Key responsibilities include proposing microarchitectural innovations for front-end, mid-end, and back-end domains, building performance models, and performing CPI/IPC analysis. The engineer will utilize AI-driven design methodologies, C/C++, Python, and simulators like gem5 to accelerate architectural exploration. The work focuses on solving performance and efficiency requirements for data center and agentic AI workloads, specifically exploring CPU-memory co-design and out-of-order execution. Candidates must possess expertise in RISC-V, ARM, or x86 cores, branch prediction, pipelines, and cache systems to drive technical strategy and hardware gains.

Skills

RISC-V ARM x86 Python C++ gem5 RTL SIMD RVV CPU Microarchitecture Silicon Validation CPI/IPC Analysis Agentic AI

What you'll do

  • Propose new microarchitectural ideas and take ownership of specific domains like front-end, mid-end, and back-end.
  • Use AI-driven design methodologies to rapidly implement and validate architectural ideas on real silicon.
  • Build, extend, and validate performance models and architectural simulators.
  • Perform CPI/IPC analysis to identify and resolve root causes of performance bottlenecks.
  • Characterize workloads and benchmarks including SPEC, server, client, and agentic AI traces.
  • Translate performance analysis and modeling results into architectural direction and design decisions.
  • Drive research leading to patents and technical publications.
  • Work with RTL design teams to translate architectural concepts into implementable designs.

What we're looking for

  • Master’s degree in Computer Engineering, Computer Science, or a related field with 8+ years of relevant experience, or a PhD with 5+ years of relevant experience.
  • 4+ years of experience in CPU microarchitecture or performance engineering.
  • Experience designing RISC-V, ARM, x86 CPU cores, or GPU/NPU vector units.
  • Strong understanding of out-of-order execution, branch prediction, pipelines, speculation, and cache/memory systems.
  • Hands-on experience with architectural simulators such as gem5.
  • Proficiency in C/C++ and Python.
  • Experience analyzing large-scale performance data and traces.
  • Experience with AI-driven or agentic design workflows, PPA trade-off analysis, or CPU tapeout (preferred).

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