Analog Layout Automation Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $175,500–$311,700 / yr
Posted: 11 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $197k

This role $244k

$126k $332k

below market most similar roles pay here above market

This role pays more than 83% of similar roles. Most pay $161,771–$233,050 — the blue band above. At the midpoint, this role pays about $244k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Analog Layout Automation Engineer

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The Analog Layout Automation Engineer joins the Silicon Engineering Group to support the development of next-generation systems-on-chip. This role involves converting design concepts into silicon by creating high-performance analog and mixed-signal layouts for SerDes, PLLs, and sensors. Key responsibilities include reviewing floor plans, running verification suites, and resolving LVS, DRC, and ERC issues. The engineer will drive automation by developing scripts, improving workflows, and applying AI/ML techniques for layout optimization, verification acceleration, and data-driven design insights. Required technical skills include proficiency in SKILL, Perl, TCL, Shell, and Python, along with experience in PyTorch, CNNs, and supervised learning. The role requires expertise in deep-submicron CMOS and FinFET technologies, Cadence Virtuoso, and Cadence Innovus to address reliability concerns like IR drop and electromigration.

Skills

Analog Layout Automation Cadence Virtuoso Python SKILL Perl TCL PyTorch DRC LVS ERC FinFET CMOS Cadence Innovus PCell DFM Image Processing

What you'll do

Convert design concepts into high-performance analog and mixed-signal layouts using advanced CAD tools.
Develop scripts in SKILL, Perl, TCL, or Python to automate layout tasks and improve workflows.
Apply AI/ML techniques to optimize layouts, accelerate verification, and generate data-driven design insights.
Review floor plans and analyze circuits to ensure proper physical integration and hierarchical assembly.
Execute verification suites and resolve LVS, DRC, and ERC issues to ensure design integrity.
Create PCells and develop productivity tooling to reduce manual effort in the layout process.
Diagnose and resolve layout-related issues involving IR drop, RC delay, and electromigration.

What we're looking for

BS degree in a relevant field.
Minimum of 10 years of relevant industry experience.
Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies (preferred).
Strong programming skills in SKILL, Perl, TCL, Shell, and/or Python for layout automation and data analysis (preferred).
Understanding of supervised/self-supervised learning, CNNs, and PyTorch for model development (preferred).
Demonstrated ability to automate layout tasks, flows, and quality checks using scripting and CAD tools (preferred).
Proficiency in custom and standard-cell floor planning, hierarchical layout assembly, and physical integration (preferred).
High proficiency in interpreting physical verification reports, including DRC, ERC, and LVS (preferred).