Analog Layout Automation Engineer

Apple Inc

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Work type: On-site
Location: Melbourne, FL
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $201k

$135k most similar roles pay here $253k

This listing doesn't post a salary. Most similar roles pay $160,947–$241,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Analog Layout Automation Engineer

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The Analog Layout Automation Engineer joins the Silicon Engineering Group to develop high-performance analog and mixed-signal circuits, including SerDes, PLLs, and sensors. This role involves converting design concepts into silicon by collaborating with circuit designers, reviewing floor plans, analyzing circuits, and resolving LVS, DRC, and ERC issues. A primary focus is driving automation through script development, workflow improvements, and the application of AI/ML techniques for layout optimization, verification acceleration, advanced modeling, and data-driven insights. The role requires proficiency in SKILL, Perl, TCL, Shell, and Python, along with experience in PyTorch, convolutional neural networks, and image processing fundamentals. Candidates will utilize Cadence Virtuoso and Innovus to manage complex layouts in deep-submicron CMOS and FinFET technologies while addressing technical challenges like IR drop, RC delay, electromigration, and self-heating within sophisticated systems-on-chip environments.

Skills

SKILL Perl TCL Shell Python PyTorch Cadence Virtuoso Cadence Innovus LVS DRC ERC AI FinFET CMOS PCell

What you'll do

Convert design concepts into high-performance analog and mixed-signal layouts using advanced CAD tools.
Develop scripts and automation tools in SKILL, Perl, TCL, Shell, or Python to improve layout workflows.
Apply AI/ML techniques for layout optimization, verification acceleration, and data-driven design insights.
Resolve physical verification issues including LVS, DRC, and ERC errors.
Perform floor planning, hierarchical layout assembly, and physical integration for complex SOCs.
Implement high-quality layouts with focus on device matching, low noise, and low power consumption.
Create PCells and automate CAD workflows to reduce manual effort in the design process.
Analyze circuit structures to address reliability concerns like IR drop, electromigration, and self-heating.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies (preferred).
Proficiency in SKILL, Perl, TCL, Shell, and/or Python for layout automation and data analysis (preferred).
Knowledge of supervised/self-supervised learning, CNNs, and core training concepts like loss functions and backpropagation (preferred).
Hands-on experience with PyTorch for model development and experimentation (preferred).
Ability to automate layout tasks, flows, and quality checks using scripting and CAD tools (preferred).
Proficiency in floor planning, hierarchical layout assembly, and physical integration (preferred).
Experience with Cadence Virtuoso features and Innovus, along with high proficiency in DRC, ERC, and LVS verification (preferred).

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