Analog Layout Automation Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Austin, TX
Posted: 1 day ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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How this pay compares to similar roles

Similar $201k

$135k most similar roles pay here $253k

This listing doesn't post a salary. Most similar roles pay $160,947–$241,750.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

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At a glance

TL;DR · Analog Layout Automation Engineer

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As an Analog Layout Automation Engineer within the Silicon Engineering Group, you will contribute to the evolution of analog and mixed-signal circuits including SerDes, PLLs, and sensors. You will collaborate with circuit designers to convert design concepts into silicon by creating high-performance layouts using advanced CAD tools. Your daily responsibilities involve reviewing floor plans, analyzing circuits, running verification suites, and resolving LVS, DRC, and ERC issues. To drive efficiency, you will develop scripts, improve workflows, and apply AI/ML techniques for layout optimization and verification acceleration. Required skills include proficiency in SKILL, Perl, TCL, Shell, and Python, along with experience in PyTorch, convolutional neural networks, and image processing. You will work with Cadence Virtuoso and Innovus to address technical challenges like IR drop, RC delay, and electromigration within complex systems-on-chip environments.

Skills

SKILL Perl TCL Shell Python PyTorch Cadence Virtuoso Cadence Innovus LVS DRC ERC AI PCell Layout Automation Floor Planning FinFET CMOS

What you'll do

Convert design concepts into high-performance analog and mixed-signal layouts using advanced CAD tools.
Develop scripts and automation tools in SKILL, Perl, TCL, or Python to improve layout workflows.
Implement AI/ML techniques for layout optimization, verification acceleration, and data-driven design insights.
Resolve LVS, DRC, and ERC issues to ensure physical verification compliance.
Perform floor planning, hierarchical layout assembly, and physical integration for complex SOCs.
Automate repetitive layout tasks and quality checks to reduce manual effort.
Analyze circuit designs to address reliability concerns like IR drop, electromigration, and coupling capacitance.
Create and manage PCells and custom automation workflows within the Cadence Virtuoso environment.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies (preferred).
Strong programming skills in SKILL, Perl, TCL, Shell, and/or Python for layout automation and data analysis (preferred).
Knowledge of machine learning concepts including CNNs, loss functions, backpropagation, and PyTorch experience (preferred).
Ability to automate layout tasks, flows, and quality checks using scripting and CAD tools (preferred).
Proficiency in floor planning, hierarchical layout assembly, and physical integration (preferred).
Experience with Cadence Virtuoso features and Cadence Innovus (preferred).
Technical understanding of physical verification (DRC, ERC, LVS) and reliability concerns like IR drop and electromigration (preferred).

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