Semicustom DFT Strategy Lead

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$234,320–$351,480 / yr
Posted
106 days ago
Freshness
Confirmed live yesterday
Closes
May 28, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $207k
This role $293k
$141k most similar roles pay here $374k

This role pays more than 92% of similar roles. Most pay $168,425–$245,303 — the shaded band above. At the midpoint, this role pays about $293k versus about $207k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 367 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 367 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Semicustom DFT Strategy Lead

As a Semicustom DFT Strategy Lead within the Central DFX group, you will drive the adoption of company-wide Design-for-Test strategies while ensuring compliance across various design stages like floor planning and timing closure. You will collaborate with SOC and PDG teams to balance conflicting goals such as schedule, power, performance, area, cost, and quality. Your daily work involves analyzing post-silicon experiments to evaluate the return on investment for DFT features, influencing partners in the EDA and ATE industries, and making build versus buy decisions for tools. You will lead teams to architect and implement internal solutions while developing a vigorous DFT roadmap. The role requires extensive knowledge of semiconductor testing, experience with industry-leading EDA and ATE tools, and expertise in creating advanced test techniques for complex APU, game console, and GPU graphics products.

What you'll do

  • Drive the adoption of and ensure compliance with company-wide DFT strategies across SOC and PDG teams.
  • Advocate for the maintenance of testability features throughout all stages of the design process.
  • Analyze post-silicon experiments to evaluate the effectiveness and return on investment of DFT features.
  • Influence and manage relationships with external partners in the EDA and ATE industries.
  • Evaluate third-party tools and make strategic "Build vs Buy" decisions for internal needs.
  • Lead teams to architect, implement, and maintain internal solutions when build decisions are made.
  • Develop and execute a vigorous DFT roadmap to keep test professionals informed and engaged.

What we're looking for

  • Extensive and senior knowledge in DFT and testing for semiconductor designs.
  • Proven ability to define a world-class DFT roadmap strategy.
  • Experience driving enterprise and cross-department collaboration across a design organization.
  • Experience partnering with industry-leading EDA and ATE companies.
  • Knowledge of current and industry-leading EDA and ATE tools.
  • Experience developing and deploying internal DFT tools successfully.
  • Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or a related field preferred.

More like this

Similar roles

Senior DFT Engineer

Nvidia

Santa Clara, CA 3 days ago $168,000$264,500
DFT ATPG ATE Scan Test VLSI RTL 2.5D/3D ICs Multi-chiplet Architecture Silicon Testing AI CAD Automated Solutions
6+ yrs exp Hybrid

DFT Methodology Engineer

Nvidia

Santa Clara, CA 7 days ago $168,000$264,500
DFT SoC Architecture RTL Design Verification Scan Memory BIST ATE STA Pattern Generation Silicon Debug Bring-up DFX I1149.1 I1500 I1687 1838
10+ yrs exp

CPU DFT Engineer

Qualcomm

Santa Clara, CA 43 days ago $142,200$213,400
DFT ATPG Mentor Tessent Verilog VHDL TCL Python Shell Scripting Perl JTAG MBIST LBIST Scan Compression IEEE 1500 VLSI Test Pattern Translation
2+ yrs exp

Senior DFT Engineer

Nvidia

Santa Clara, CA 23 days ago $196,000$310,500
DFT IEEE1149.1 IEEE1500 SSN Scan Compression IOBIST Memory BIST ATE Python DDR HBM Failure Analysis LVP Photon Emission ebeam probing Advantest 93k
10+ yrs exp Hybrid

DFT Lead Engineer

Broadcom

San Jose, CA 31 days ago $143,800$230,000
DFT ATPG Scan Compression MBIST Tessent SSN Mentor TestKompress TetraMax Fastscan Verilog TCL Python C++ Perl Ruby STA IEEE1149.1 IEEE1149.6 IEE1687 IJTAG ICL PDL ATE
10+ yrs exp

Senior DFT Engineer

Nvidia

Santa Clara, CA 7 days ago $168,000$264,500
DFT BIST Scan Compression ATPG Fault Simulation RTL STA VLSI Python Perl Tcl Silicon Debug ATE ISO26262 ASIC Design
8+ yrs exp Hybrid