Semicustom DFT Strategy Lead

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$234,320–$351,480 / yr
Posted
151 days ago
Freshness
Confirmed live yesterday
Closes
May 28, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $218k
This role $293k
$146k $373k
below market most similar roles pay here above market

This role pays more than 92% of similar roles. Most pay $181,500–$254,750 — the blue band above. At the midpoint, this role pays about $293k versus about $218k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · Semicustom DFT Strategy Lead

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The Semicustom DFT Strategy Lead joins the Central DFX group to optimize and standardize design methodology for complex APU computing, game console, and GPU graphics products. This senior leader will drive the adoption of company-wide DFT strategies, ensuring compliance across SOC and PDG teams while advocating for testability features during floor planning and timing closure. Key responsibilities include analyzing post-silicon experiments to determine return on investment, influencing EDA and ATE industry partners, and making build versus buy decisions for internal tools. The successful candidate will architect and manage the implementation of internal solutions and maintain a vigorous DFT roadmap. Required expertise includes extensive knowledge of semiconductor testing, experience with industry-leading EDA and ATE tools, and the ability to manage cross-departmental collaboration to balance schedule, power, performance, area, and quality.

Skills

DFT Design-for-Test Design-for-Debug EDA ATE ASIC Design CAD Automation Floor Planning Timing Closure DFT Roadmap Power/Performance/Area DPPM

What you'll do

  • Drive adoption of and ensure compliance with the company-wide DFT strategy across SOC and PDG teams.
  • Advocate for the maintenance of testability features during floor planning and timing closure stages.
  • Analyze post-silicon experiments to evaluate the effectiveness and return on investment of DFT features.
  • Influence and manage relationships with external EDA and ATE industry partners.
  • Evaluate external tools to make "Build vs Buy" decisions for the organization.
  • Lead teams to architect, implement, and deploy internal DFT solutions and maintenance.
  • Develop and execute a vigorous DFT roadmap to keep test professionals informed and engaged.

What we're looking for

  • Extensive and senior knowledge in DFT and testing for semiconductor designs (preferred).
  • Proven ability and experience with defining a world-class DFT roadmap strategy (preferred).
  • Proven ability to drive enterprise and cross-department collaboration for DFT across a design organization (preferred).
  • Proven ability and experience partnering with industry leading EDA and ATE companies (preferred).
  • Knowledge with current and industry leading EDA and ATE tools (preferred).
  • Experience developing and deploying internal DFT tools successfully (preferred).
  • Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or a related field (preferred).

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