RTL Design Engineer

The RTL Design Engineer joins the mixed-signal silicon design team to develop, specify, and micro-architect digital and signal processing blocks within sophisticated mixed-signal circuits. This role involves translating DSP concepts like filtering, transforms, and modulation into high-performance RTL implementations while ensuring formal equivalence between custom designs and abstract representations. The engineer will perform RTL coding in Verilog and SystemVerilog, write comprehensive assertions for verification, and support lab bring-up by writing test scripts and analyzing data to validate signal processing performance. Key technical skills include proficiency with front-end tools, synthesis, static timing analysis, and design-for-test methodologies. Candidates should possess experience in Perl or Python scripting, hardware-software co-design, and advanced GenAI proficiency for SystemVerilog optimization. The role focuses on integrating high-performance mixed-signal IPs into high-speed digital circuits to solve complex signal processing challenges.