Quantum Systems Digital Design Engineer II

What you'll do

• Design and implement RTL for streaming, low-latency pipelines in Verilog or SystemVerilog.
• Implement high-speed interconnects including AXI4, JESD204, Aurora, and PCIe protocols.
• Develop robust clocking and CDC strategies to ensure deterministic performance across multi-domain systems.
• Define hardware/firmware boundaries such as register maps, DMA models, and driver interfaces.
• Create simulation testbenches using SV/UVM and perform lab bring-up with RF instruments.
• Manage synthesis, timing sign-off, and automated build scripts using Tcl or Python.
• Develop hardware accelerators for real-time algorithms like decoders, filtering, or classification.

What we're looking for

• Master's degree in Physics or Engineering with 1+ years of experience, or a Bachelor's degree with 2+ years of experience.
• 3+ years of experience building production FPGA designs in Verilog/SystemVerilog (or VHDL) on Xilinx/AMD or Intel platforms.
• Experience designing low-latency streaming datapaths and high-speed I/O protocols including AXI4, JESD204(B/C), Aurora, and multi-gig SERDES.
• Proficiency in clocking and CDC fundamentals for multi-clock, multi-reset systems.
• Experience with verification (simulation, assertions, UVM) and lab debug using ILA, scopes, and RF test gear.
• Ability to work across hardware/software boundaries including DMA tuning, driver interfaces, and gRPC/REST control surfaces.
• Must be a U.S. Person (citizen, permanent resident, or protected status) to meet export control requirements.
• US citizenship, as indicated in the job description, a valid US passport.