Quantum Systems Digital Design Engineer II

What you'll do

• Design and implement RTL for low-latency streaming pipelines using Verilog or SystemVerilog.
• Develop high-speed interconnects including AXI4, JESD204, Aurora, and PCIe protocols.
• Design robust clocking and CDC strategies for multi-domain timing closure and metastability analysis.
• Co-design hardware/firmware/software boundaries including register maps, DMA, and interrupt models.
• Develop simulation and constrained-random tests using SV/UVM and build on-board diagnostics.
• Execute lab bring-up using oscilloscopes, VNAs, and other RF instruments.
• Own the synthesis, implementation, and timing sign-off flow using Vivado, Vitis, or Quartus.
• Create scripted builds using Tcl or Python integrated with Git and Azure DevOps CI/CD.

What we're looking for

• Master's degree in Physics, Electrical/Computer Engineering, or related field with 1+ years of industry or R&D experience.
• Bachelor's degree in Physics, Electrical/Computer Engineering, or related field with 2+ years of industry or R&D experience.
• 3+ years of experience building production FPGA designs in Verilog/SystemVerilog (or VHDL) including synthesis, P&R, and static timing analysis.
• Proven experience delivering low-latency, streaming datapaths with tight timing closure at high clocks.
• Proficiency in high-speed I/O protocols including AXI4/AXIS, JESD204(B/C), Aurora, and multi-gig SERDES.
• Proficiency in clocking and CDC fundamentals for multi-clock, multi-reset systems.
• Proof of citizenship or U.S. permanent residency/protected status for export control regulations (ITAR/EAR).
• US citizenship, as indicated in the job description, a valid US passport.