SerDes System Validation Engineer

As a SerDes System Validation Engineer, you will join the Analog-Mixed/Signal design team to perform critical validation and debug of embedded circuits. You will take ownership of SerDes system bring-up in a system environment, where you will verify operations, analyze robustness and margins, and collaborate with design teams to define DFT needs for improved testability and first-time silicon success. Your work involves mixed-signal verification tasks to ensure pre-silicon test coverage and the development of features for in-situ validation. The role requires expertise in high-speed serial links, including protocols like PCIe, USB, DP, and MPHY, as well as knowledge of Tx/Rx equalization techniques such as CTLE, DFE, and de-emphasis. You will utilize skills in scripting, automation, and potentially AI/ML concepts to enhance silicon performance and improve the efficiency of the design and validation process.