Principal System Power Management and Performance Architect

What you'll do

• Develop multi-generation roadmaps for system-level power and performance features based on prototyping and use-case analysis.
• Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features.
• Lead system-level boot and IST architecture to define how power and clock domains initialize across multi-IP systems.
• Drive datacenter-scale power management strategies including rack-level telemetry and platform state coordination.
• Redesign system-level processes such as boot/reset flows and low-power entry/exit sequences that fail under new requirements.
• Serve as the technical authority to influence power-performance trade-offs across ASIC, board, and firmware teams.
• Resolve complex performance gaps and power anomalies by building frameworks rather than just addressing single instances.

What we're looking for

• BS or MS in EE/CE, or equivalent experience proven through the work itself.
• 15+ years of system architecture, development, and validation experience with a focus on power and performance-per-watt optimization.
• Verifiable history of guiding architecture decisions that shipped across multiple silicon programs.
• Extensive knowledge of HSIO power management, DVFS, P-states, system boot flows, and low-power entry/exit architecture.
• Strong fundamentals in low-power design, power management techniques, and rack-level performance architecture.
• Practical, hands-on depth in at least two of the following: system power management, robust boot flow optimizations, HSIO, or memory power management (preferred).
• A power management architecture or methodology introduced by the candidate that survived multiple silicon generations and was adopted beyond their immediate team (preferred).
• Demonstrated AI/agentic workflow practice to compress engineering velocity while applying strong judgment to validate results (preferred).