below marketmost similar roles pay hereabove market
This role pays more than
94%
of similar roles. Most pay
$172,350–$255,000
— the blue band above.
At the midpoint, this role pays about
$300k
versus about
$214k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1623 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 1110 roles with salary data.
The Principal System Power Management and Performance Architect joins the Silicon Co-Design Group to address complex power anomalies and performance gaps. This role involves defining multi-generation roadmaps for system-level power and performance features, owning the architecture for HSIO power management, DVFS, P-states, and low-power features. The architect will lead system-level boot and IST architecture, managing how power and clock domains initialize across multi-IP systems. Key responsibilities include driving datacenter-scale power management strategies, including rack-level power telemetry and platform state coordination. Candidates must possess deep expertise in low-power design, system boot flows, and power-performance trade-offs. The role requires navigating the intersection of workload behavior, silicon capabilities, firmware policies, and platform constraints to ensure reliability and performance across multiple silicon generations in high-performance environments.
Define the multi-generation roadmap for system-level power and performance features based on prototyping and cost-benefit trade-offs.
Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features.
Lead system-level boot and IST architecture to define power and clock domain initialization, sequencing, and recovery.
Drive power management strategy at datacenter scale, including rack-level power telemetry and platform state coordination.
Redesign system-level processes such as boot/reset flows and low-power entry/exit sequences that fail under new requirements.
Diagnose why prior designs no longer hold and architect next-generation solutions to address those failures.
Serve as the multi-functional technical authority for architecture, ASIC, board/platform, and firmware teams.
Influence decisions made by external teams to improve power-performance trade-offs across the product line.
What we're looking for
BS or MS in EE/CE, or equivalent experience proven through the work itself.
15+ years of system architecture, development, and validation experience with a focus on power and performance-per-watt optimization.
Verifiable history of guiding architecture decisions that shipped across multiple silicon programs.
Extensive knowledge of HSIO power management, DVFS, P-states, system boot flows, and low-power entry/exit architecture.
Strong fundamentals in low-power design, power management techniques, and rack-level performance architecture.
Practical, hands-on depth in at least two of the following: system power management, robust boot flow optimizations, HSIO, and memory power management (preferred).
A power management architecture or methodology introduced by the candidate that survived multiple silicon generations and was adopted beyond their immediate team (preferred).
Demonstrated AI/agentic workflow practice and visible technical leadership through patents, publications, or industry recognition (preferred).
Silicon Power Architecture
System-level Design
Digital Design
Low Power Design
DVFS
Control Systems
Power Management
C/C++
Python
Perl
Linux
Windows
Firmware
ASIC
Oscilloscope
Logic Analyzer
GitHub Copilot
Claude
Silicon Power and Thermal Controllers
Firmware
DVFS
Power Characterization
Performance Analysis
Digital Design
Circuit Analysis
CPU/GPU/SoC Architecture
PTPX
data-analysis
Statistics
AI Productivity Tools
Validation
ATE
AI Compute Platforms
SoC
CPU
GPU
AI Accelerators
Power Management
Thermal Solutions
Silicon Architecture
Firmware
Operating Systems
Workload Characterization
Power Delivery Systems
Liquid Cooling
Azure
Datacenter Infrastructure
hardware, validation
Pre-silicon Validation