Senior Power and Performance Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
34 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k
This role $216k
$126k $279k
below market most similar roles pay here above market

This role pays more than 78% of similar roles. Most pay $152,150–$216,250 — the blue band above. At the midpoint, this role pays about $216k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Power and Performance Engineer

The Senior Power and Performance Engineer joins the Silicon Co-design Group ArchDev team to manage the full product development lifecycle from architecture definition through silicon bringup. This role involves architecting and integrating system-level performance and power management features, controllers, and policies to optimize efficiency across datacenter and client products. Key responsibilities include building feature roadmaps for low-power and performance-per-watt needs, conducting use-case analysis, and leading debug efforts for complex issues. The position requires expertise in silicon power architecture, digital design, DVFS, control systems, and HW/SW interaction. Candidates must possess programming proficiency in C/C++, Python, or Perl and experience with lab tools like oscilloscopes and logic analyzers. The work focuses on solving technical tradeoffs between power, noise, and performance within silicon and system-level designs.

What you'll do

  • Architect and integrate system-level performance and power management features, controllers, and policies.
  • Build feature roadmaps to address low-power, low-noise, and performance-per-watt product needs.
  • Conduct prototyping, use-case analysis, and cost/benefit trade-offs for product efficiency.
  • Drive design decisions and debug complex issues across architecture, ASIC, board, and software teams.
  • Translate industry trends and market needs into forward-looking product roadmaps.
  • Lead debug efforts and develop workarounds for bringup, validation, manufacturing, and customer escalations.

What we're looking for

  • BS or MS in EE/CE or equivalent experience.
  • 8+ years of experience in silicon power architecture, system-level design, validation, and power/performance optimization.
  • Strong EE fundamentals in digital design, low power design, DVFS, control systems, power management, timing, and architecture.
  • Solid understanding of firmware/driver structures and HW/SW interaction.
  • Programming proficiency in C/C++, Python, or Perl in Windows/Linux environments.
  • Familiarity with clocking, boot/reset flows, and system architecture (preferred).
  • Hands-on lab experience with oscilloscopes, multimeters, logic analyzers, and silicon bringup exposure (preferred).
  • Demonstrated cross-functional leadership and system-level intuition (preferred).

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