Principal IC Verification Engineer

Broadcom

Quick summary

Work type
On-site
Location
Broomfield, CO · Mendota Heights-Northland · Fort Collins, CO
Salary
$127,100–$203,400 / yr
Posted
51 days ago
Closes
Aug 29, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $189k
This role $165k
$116k most similar roles pay here $229k

This role pays less than 72% of similar roles. Most pay $161,125–$216,250 — the shaded band above. At the midpoint, this role pays about $165k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Principal IC Verification Engineer

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The ASIC Product Division at Broadcom seeks a senior verification engineer to join its high-performance design team focused on developing state-of-the-art subsystems for AI and storage chips. The role involves advanced verification tasks such as environment development using System Verilog and UVM, designing verification components like UVM agents, implementing coverage and assertions, and creating random and directed test cases. Daily responsibilities include analyzing simulation failures and coverage results to ensure robust design validation. Ideal candidates possess expertise in HDL languages (Verilog/VHDL/SystemVerilog), constrained random environments using UVM/OVM/VMM, and OOP techniques with C++ or Java. Strong communication skills and the ability to lead independently on complex projects are essential for success in this fast-paced environment.

Skills

SystemVerilog UVM Verilog VHDL C++ Java OOP HDL simulators

What you'll do

  • Develop verification environments using System Verilog and UVM.
  • Design verification components such as UVM agents and behavioral models.
  • Implement coverage and assertions using System Verilog.
  • Analyze and debug simulation failures for subsystems.
  • Develop random and directed test cases based on specifications.

What we're looking for

  • Demonstrated expertise in SystemVerilog and UVM for verification.
  • Experience designing constrained random environments using UVM/OVM/VMM.
  • Proficiency in HDL simulators and debugging techniques.
  • Strong background in OOP languages (C++, Java) and object-oriented design.
  • Ability to conceive and develop innovative solutions for complex problems.
  • Bachelors in EE, CE, or CS with 12+ years of related experience, or Masters with 10+ years.
  • Excellent communication and leadership skills in a matrix organization.

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