Silicon Design Verification Engineer in San Jose, California | Advanced Micro Devices, Inc

Amd

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$166,400–$166,400 / yr
Posted
94 days ago
Closes
Mar 9, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $166k
$153k most similar roles pay here $229k

This role pays less than 71% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $166k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 71 open roles on FindRole.

Listed pay typically runs $178,400–$178,400 across 71 roles with salary data.

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View all roles at Amd

At a glance

TL;DR · Silicon Design Verification Engineer in San Jose, California | Advanced Micro Devices, Inc

As a senior verification engineer on AMD’s FPGA team, you will lead the functional correctness and quality assurance of new and existing features for advanced processor devices. Your daily tasks include collaborating with architects and hardware engineers to develop comprehensive test plans, estimating test development time, building directed and random verification tests, debugging failures, and ensuring coverage metrics meet requirements. Ideal candidates have strong experience in UVM-based verification environments, proficiency in SystemVerilog, Verilog, C, and C++, scripting skills with Python, and a solid understanding of UVM concepts and SystemC. This role involves working on large-scale digital subsystems to deliver robust designs for complex business problems in the semiconductor industry.

What you'll do

  • Develop comprehensive verification strategies for AMD’s FPGA devices.
  • Create detailed test plans considering interactions with other features and environments.
  • Estimate time requirements for writing new feature tests and modifying test environments.
  • Build directed and random verification tests to ensure functional correctness.
  • Debug test failures to identify root causes and resolve design defects collaboratively.

What we're looking for

  • Strong analytical and debugging skills for complex digital subsystems.
  • Experience developing UVM-based verification environments and testbenches.
  • Proficiency in SystemVerilog, Verilog, C, and C++.
  • Scripting experience with Python or similar automation languages.
  • Good understanding of UVM concepts and SystemVerilog language.

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