Senior System Integration and Validation Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
11 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $184k
This role $216k
$128k most similar roles pay here $279k

This role pays more than 79% of similar roles. Most pay $154,425–$214,562 — the shaded band above. At the midpoint, this role pays about $216k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1371 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1096 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior System Integration and Validation Engineer

Senior System Integration and Validation Engineer The Senior System Integration and Validation Engineer joins the Silicon Co-Design Group to lead system validation, debug, and cross-functional alignment for high-stakes silicon programs. This role focuses on identifying critical silicon and platform issues before they reach customers by shifting validation coverage left through stress testing, PVT, and feature-interaction tests. You will own end-to-end system validation for GPU, SoC, and platform programs while leading the debug of complex cross-stack issues involving logic, signal integrity, power delivery, firmware, and software interactions. Key responsibilities include developing test plans, scripts, and automation for next-generation chips and building AI-enabled validation workflows with robust guardrails. You will collaborate with global teams to resolve multi-team failures and translate technical risks into decision-ready options. Required expertise includes high-speed I/O, power delivery, thermal management, and experience with GPU or SoC architectures.

What you'll do

  • Own end-to-end system validation for GPU, SoC, and platform programs including feature checks and multi-unit fleet testing.
  • Lead the debug of complex cross-stack issues involving logic, signal integrity, power delivery, firmware, and software interactions.
  • Develop test plans, scripts, and automation to translate architecture and boot flows into executable coverage before physical builds.
  • Design and deploy AI-enabled debug and validation workflows with established guardrails to improve cycle time and debug velocity.
  • Translate complex silicon and system risks into clear, decision-ready options for technical and executive audiences.
  • Lead crisis-mode debug task forces to resolve program blockers and convert findings into reusable methodologies for other teams.
  • Partner with globally distributed engineering teams to align on hardware, firmware, and manufacturing requirements.

What we're looking for

  • Hold a BTech/BE or MTech/ME in Electronics, Electrical, or Computer Engineering (or equivalent experience).
  • Have 8+ years of post-silicon validation, system integration, or platform debug experience on shipped GPU, CPU, or SoC products.
  • Possess hands-on debug depth across silicon, board, and software boundaries including logic design, signal integrity, power delivery, high-speed I/O, and PVT behavior.
  • Demonstrate strong EE fundamentals in SI/PI, power delivery, and thermal with an understanding of GPU, CPU, or SoC architecture.
  • Provide a specific example of taking an ambiguous, multi-team failure to root-cause closure with a productized fix.
  • Show a track record of leading a project team end-to-end through a crisis with owned decision points.
  • Demonstrate a built or scaled AI-driven validation workflow with measurable impact on debug velocity, coverage, or escape rate.
  • Experience in HBM, SerDes, advanced packaging, or building reusable validation methodologies (preferred).

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