Senior Manager, Silicon Speed Productization

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$232,000–$368,000 / yr
Employment
Full-time
Posted
4 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $221k
This role $300k
$144k most similar roles pay here $392k

This role pays more than 93% of similar roles. Most pay $180,500–$260,662 — the shaded band above. At the midpoint, this role pays about $300k versus about $221k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1150 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 912 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior Manager, Silicon Speed Productization

Senior Manager, Silicon Speed Productization joins the Silicon Co-Design Group to lead a team focused on the transition from design to production for GPU, CPU, and SoC programs. The role involves owning simulation-to-silicon speed correlation, identifying where predictions diverge from measured silicon, and driving root-cause closure for complex failures in frequency, voltage, and timing. You will define product limits through margin analysis, guardbanding, and binning while feeding insights back into timing models and design practices. Key responsibilities include building automated workflows using Python, JMP, and SQL to improve test orchestration and anomaly detection. The position requires deep expertise in digital design, computer architecture, static timing analysis, and semiconductor process variation. You will manage a distributed team of engineers and first-line managers to ensure products meet performance goals across various temperature and workload conditions.

What you'll do

  • Own the simulation-to-silicon speed correlation from pre-silicon planning through production sign-off for GPU, CPU, and SoC programs.
  • Drive root-cause closure for complex speed failures including frequency misses, high operating voltages, and timing analysis escapes.
  • Establish technical bases for product limits, guardbands, binning, and production decisions based on PVT characterization data.
  • Feed measured silicon insights back into timing models and design practices to improve future architecture correlation.
  • Translate complex characterization data and yield trends into decision-ready options for senior leadership.
  • Develop automated and AI-assisted workflows for test orchestration, anomaly detection, and reporting to improve cycle time.
  • Hire, develop, and lead a high-performing team of engineers and first-line managers in a global environment.

What we're looking for

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Systems Engineering (or equivalent experience).
  • Experience in silicon characterization, post-silicon validation, timing, or performance analysis.
  • 5+ years of experience leading technical teams.
  • Proven management experience developing senior engineers and first-line managers.
  • Deep technical foundation in digital design, computer architecture, static timing analysis, and semiconductor process variation.
  • Hands-on expertise with silicon speed characterization, simulation-to-silicon correlation, and voltage-frequency margining.
  • Proficiency with data-analysis and automation tools such as Python, JMP, or SQL.
  • Strong written and verbal communication skills to translate complex technical issues into decision-ready options for leadership.

More like this

Similar roles

Senior Silicon Product Definition Engineer

Nvidia

Santa Clara, CA 10 days ago $168,000–$264,500
Python Perl SQL JMP BIOS Firmware Drivers Circuit Analysis Computer Architecture data-analysis Silicon Characterization Digital Design
8+ yrs exp Hybrid

Senior Technical Program Manager, Silicon Co-Design

Nvidia

Santa Clara, CA 10 days ago $200,000–$322,000
SoC Silicon Hardware Bring-up Validation Tape-out Productization AI Inference Infrastructure Program Management Dependency Tracking Logistics Tracking Technical Program Management
10+ yrs exp Hybrid

Principal Chip Lead

Nvidia

Santa Clara, CA 10 days ago $232,000–$368,000
SoC ASIC HBM SerDes High-speed I/O Power and Thermal Packaging Post-silicon Bring-up Silicon Validation System Integration Co-design AI Tools
10+ yrs exp Hybrid

Senior Manager Silicon Design Engineering

Amd

Austin, TX +2 45 days ago $186,400–$279,600
UVM System Verilog C-DPI FPGA ASIC Firmware SoC AXI AHB DMA Cryptography Data Compression Silicon Bring-up Emulation Micro-architecture
Hybrid