Power Analysis and Optimization Engineer

Amd

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Austin, TX
Salary
$115,760–$173,640 / yr
Posted
8 days ago
Freshness
Confirmed live yesterday
Closes
Sep 23, 2027

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k
This role $145k
$99k most similar roles pay here $269k

This role pays less than 93% of similar roles. Most pay $168,500–$233,400 — the shaded band above. At the midpoint, this role pays about $145k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 374 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 374 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · Power Analysis and Optimization Engineer

As a Power Analysis and Optimization Engineer, you will join the team to perform Datacenter Server SOC power management feature optimization, power characterization, and product definition. You will collaborate with silicon, power architect, firmware, and platform teams to evaluate features in the pre-silicon phase while developing test plans for post-silicon tuning and characterization. Your daily work involves optimizing performance, finalizing fuse recipes with manufacturing teams, and managing binning strategies. The role requires expertise in computer hardware architecture including x86, PCIe, and memory, alongside software knowledge of drivers and BIOS. You will utilize programming languages like C/C++, Python, or Perl to debug at the SoC and system levels. Experience with Linux and Windows Server environments is required, along with familiarity with lab equipment such as oscilloscopes and logic analyzers to solve complex power management challenges.

What you'll do

  • Coordinate with silicon, power architect, firmware, and platform teams to evaluate power management features in the pre-silicon phase.
  • Develop comprehensive test plans for post-silicon power management feature tuning and characterization.
  • Perform post-silicon power management feature tuning to optimize product power and performance.
  • Execute post-silicon power characterization and correlation tasks.
  • Collaborate with manufacturing teams to optimize and finalize fuse recipes for product definition.
  • Debug hardware issues at both the SoC and system levels.
  • Develop validation methodologies and infrastructure for server products.

What we're looking for

  • Bachelor's degree or higher in Electrical/Computer Engineering, Electronics, or Computer Science related fields.
  • Minimum of a couple of years of experience in SoC validation and debug.
  • Knowledge of computer hardware architecture (CPU/APU, x86, PCIe, memory, bus logic) and software architecture (driver, bios, firmware).
  • Experience with power management feature enablement, optimization, and manufacturing binning strategies.
  • Proficiency in programming or scripting languages such as C/C++, Python, or Perl.
  • Working knowledge of Server OSes including Linux and Windows Server.
  • Debug skills at both SoC and system levels.
  • Working knowledge of lab equipment like NIDAQ, oscilloscopes, and logic analyzers (preferred).

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