Senior Power Analysis and Optimization Engineer

Nvidia

Confirmed live today High trust

Quick summary

Work type
On-site
Location
Santa Clara, CAAustin, TX
Salary
$136,000–$218,500 / yr
Employment
Full-time
Posted
11 days ago
Freshness
Confirmed live today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $201k
This role $177k
$123k $256k
below market most similar roles pay here above market

This role pays less than 62% of similar roles. Most pay $168,500–$233,400 — the blue band above. At the midpoint, this role pays about $177k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Power Analysis and Optimization Engineer

The Senior Power Analysis and Optimization Engineer joins the team to improve energy efficiency for GPUs and Tegra SoCs. This role involves analyzing full-chip and unit-level power using RTL and gate-level tools to drive architectural improvements. You will develop power-aware models and productionize flows using machine learning, reinforcement learning, and large language models for anomaly detection and design-space exploration. Key responsibilities include training LLMs to interpret power data, prototyping architectural features in Verilog, and automating pipelines using Python, Perl, and C++. You will collaborate with cross-functional teams to root-cause power bugs and optimize energy consumption across various workloads. The work focuses on applying data-driven AI models to power architecture, specifically addressing the challenges of scaling AI and graphics workloads in accelerated computing.

What you'll do

  • Analyze full-chip and unit-level power using RTL and gate-level tools to drive architectural improvements.
  • Develop and productionize power-aware models using ML and reinforcement learning for anomaly detection and design-space exploration.
  • Train and deploy custom LLMs to interpret complex power data and recommend architectural optimizations.
  • Perform comparative power analysis across various workloads and products to identify non-obvious trends and anomalies.
  • Prototype and evaluate new architectural features in Verilog with a focus on power and energy implications.
  • Automate power analysis flows and pipelines using Python, Perl, and C++ to fast-track anomaly detection.
  • Build data-driven models to automatically tune power-efficient configurations and policies for GPUs and SoCs.

What we're looking for

  • Master's degree and experience in EE/CE/CS or related fields.
  • PhD and experience in EE/CE/CS or related fields.
  • Strong understanding of energy consumption, power estimation, data movement, and low-power design.
  • Familiarity with Verilog and ASIC design principles.
  • Hands-on experience with tools such as PowerArtist, PrimePower/PrimePower RTL, RTL Architect, or similar.
  • Solid coding and automation skills in Python, Perl, and C++.
  • Experience or strong interest in machine learning, reinforcement learning, and data analytics applied to EDA or architecture (preferred).
  • Interest or experience in building and using LLMs or foundation models as engineering copilots (preferred).

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