Physical Design Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $262,500–$394,000 / yr
Posted: 16 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k

This role $328k

$121k most similar roles pay here $423k

This role pays more than 99% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $328k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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As a Physical Design Engineer, you will join a team focused on high-performance PHY design efforts, collaborating with architecture, CAD, timing, and logic design teams. You will manage the full physical design lifecycle from RTL through GDSII delivery. Key responsibilities include generating block and chip level static timing constraints, building full chip floorplans including pin placement and power grids, and developing low-power clock network guidelines. You will perform place and route to meet timing, area, and power constraints while implementing ECOs to resolve noise and EM IR violations. The role requires expertise in physically aware synthesis, extraction, and STA methodologies. Required skills include proficiency in Verilog, Perl, and Tcl scripting, alongside experience with industry-standard physical design and synthesis tools to navigate complex SoC architecture and physical verification flows.

What does a Physical Design Engineer earn?

Median $179650 from 40 postings across 9 companies.

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Skills

Physical Design RTL GDSII Floor-planning Place and Route STA LVS DRC Verilog Perl Tcl Synthesis Power Grid SoC Architecture Extraction

What you'll do

Generate block and chip level static timing constraints.
Build full chip floorplans including pin placement, partitions, and power grids.
Develop and validate high performance, low power clock network guidelines.
Perform block level place and route to meet timing, area, and power constraints.
Implement ECOs to resolve timing, noise, and EM IR violations.
Execute physical design verification flows and provide guidance for LVS/DRC violations.
Establish CAD and physical design methodologies for correct by construction designs.
Assist in the development of flow processes for chip integration.

What we're looking for

Bachelor of Science degree and at least 20 years of relevant industry experience.
Experience in high PHY and/or SOC designs (preferred).
Deep knowledge of Physical Design standards, including physically aware synthesis, floor-planning, and place and route (preferred).
Experience developing and implementing power-grid and clock specifications (preferred).
Strong understanding of physical construction, integration, and physical verification (preferred).
Knowledge of basic SoC architecture and HDL languages like Verilog (preferred).
Power user of industry standard Physical Design and Synthesis tools (preferred).
Deep understanding of scripting languages like Perl/Tcl, extraction, STA methodology, and verification methods (preferred).