PHY RTL Design Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$129,300–$225,300 / yr
Posted
113 days ago
Freshness
Confirmed live today

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $177k
$115k most similar roles pay here $262k

This role pays less than 60% of similar roles. Most pay $168,500–$231,300 — the shaded band above. At the midpoint, this role pays about $177k versus about $200k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3683 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2845 roles with salary data.

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At a glance

TL;DR · PHY RTL Design Engineer

The PHY RTL Design Engineer joins the wireless silicon development team to develop signal processing intensive designs for wireless communication SoCs. The role involves writing specifications, defining microarchitecture based on MATLAB/C system models, and architecting area and power for efficient low latency designs. Daily responsibilities include RTL coding and verification for PHY modem development, supporting backend activities through report reviews, and participating in pre- and post-silicon bringup processes. Candidates must possess knowledge of DSP fundamentals, digital communications, and fixed-point logic. Technical requirements include proficiency in RTL design, experience with AXI/AHB/APB bus fabrics, and familiarity with UVM environments. The work focuses on solving complex wireless protocol challenges involving Viterbi, LDPC, or Polar decoders while ensuring energy-efficient designs through advanced power management across multiple domains for high-performance wireless hardware.

What you'll do

  • Write specifications and define microarchitecture based on MATLAB/C system models.
  • Architect area and power for signal processing intensive designs in wireless communication SoCs.
  • Design low-latency, scalable, and flexible RTL logic for wireless protocols.
  • Perform synthesis, timing constraints, and run tools to ensure lint and CDC/RDC clean designs.
  • Execute RTL coding and verification for PHY modem development.
  • Review backend reports and perform necessary design adjustments to support physical implementation.
  • Participate in the pre-silicon and post-silicon bringup processes.

What we're looking for

  • Bachelor's degree in a related field.
  • Understanding of DSP fundamentals.
  • Knowledge of digital communications.
  • Proficiency in RTL design.
  • Familiarity with UVM DV environment and AI based efficiency improvement flows (preferred).
  • Strong fixed-point knowledge and experience with bit-true cycle-accurate verifications (preferred).
  • Understanding of decoders, filter design, and multi-radix implementation (preferred).
  • Knowledge of modern energy-efficient logic design, power analysis, and wireless standards (preferred).

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