NoC Interconnect Design Engineer and Architect

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$164,000–$246,000 / yr
Posted
3 days ago
Closes
Dec 27, 2026

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Salary context

Competitive pay

How this pay compares to similar roles

Similar $195k
This role $205k
$141k most similar roles pay here $257k

This role pays more than 57% of similar roles. Most pay $166,012–$223,700 — the shaded band above. At the midpoint, this role pays about $205k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 533 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 513 roles with salary data.

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At a glance

TL;DR · NoC Interconnect Design Engineer and Architect

The NoC bus team at Qualcomm Technologies seeks a senior architect to drive micro-architecture choices and design guidelines for bus protocol compliance in large-scale SoCs. This role involves creating detailed specifications for bus components, analyzing performance results, delivering RTL code, and running tool flows. The candidate will also evaluate new IPs, define system-wide interconnect guidelines, and collaborate with verification, silicon validation, and software teams to ensure successful deployments. Ideal candidates possess expertise in various bus protocols like AHB, AXI, and CHI, as well as a strong understanding of ASIC flow tools including synthesis, timing analysis, and power management. Proficiency in RTL design, FPGA debugging, and post-silicon troubleshooting is essential, along with the ability to quickly adapt to changes and define micro-architectures balancing performance, power, and area trade-offs.

What you'll do

  • Define micro-architecture for bus components considering performance, power, and area trade-offs.
  • Analyze performance results to identify architecture bottlenecks and drive micro-architecture choices.
  • Evaluate new IPs and drive the deployment of new protocols within SoC projects.
  • Provide design guidelines for IP inter-operation in large-scale SoCs.
  • Deliver RTL code and support verification and silicon validation teams.
  • Collaborate with software teams to ensure successful deployment of interconnects.

What we're looking for

  • Strong knowledge of bus protocols such as AHB, AXI, and CHI.
  • Experience with VLSI design and ASIC flow including synthesis and power tools.
  • Ability to analyze architecture trade-offs for performance, power, and area.
  • Successful deployment experience with IPs in large SoC projects.
  • Proficiency in RTL design, FPGA debugging, and post-silicon validation.
  • Collaborative work style in a multi-disciplinary team environment.
  • Troubleshooting skills and adaptability to changing project requirements.

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