Digital Mixed Signal Modeling Verification Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$184,700–$324,800 / yr
Posted
4 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $205k
This role $255k
$129k most similar roles pay here $346k

This role pays more than 97% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $255k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3518 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2727 roles with salary data.

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At a glance

TL;DR · Digital Mixed Signal Modeling Verification Engineer

The Digital/Mixed Signal Modeling/Verification Engineer joins the Hardware Technology organization to verify the functionality and performance of premier SOCs. In this role, you will own the modeling and verification of advanced analog and RF blocks, such as regulators, bandgaps, data converters, LNAs, PAs, mixers, and PLLs within a large SoC. Your daily responsibilities include developing RNM models in SystemVerilog with self-checking techniques, creating assertions to ensure analog and digital specifications are met, and collaborating with analog designers to set up AMS simulation environments. You will also debug complex chip digital-on-top testbenches to identify root causes for failures. The role requires expertise in RNM coding in SystemVerilog, strong fundamentals in analog/RF circuit theory, and experience with Cadence mixed signal verification environments to solve critical integration challenges within the SoC architecture.

What you'll do

  • Develop RNM RF and analog models using SystemVerilog.
  • Create self-checking models for various analog and RF blocks within a large SoC.
  • Determine the required model accuracy levels based on specific verification goals.
  • Develop assertions to ensure analog and digital specifications are met.
  • Collaborate with analog designers to set up AMS simulation environments.
  • Debug complex chip digital-on-top testbenches to identify root causes for failures.

What we're looking for

  • Bachelor of Science degree and at least 10 years of relevant industry experience.
  • Expert proficiency in RNM coding using SystemVerilog.
  • Strong fundamentals in analog and RF circuit theory and topologies.
  • Master of Science degree and 7 years of relevant industry experience (preferred).
  • Experience working with the Cadence mixed signal verification environment (preferred).
  • Ability to read analog schematics and extract main functionality (preferred).
  • Experience modeling various mixed signal/RF blocks including regulators, data converters, and PLLs (preferred).

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