Mixed Signal Verification Engineer

As a Mixed Signal Verification Engineer within the Hardware Technology organization, you will be responsible for verifying the functionality and performance of premier SOCs. You will own the modeling and verification of analog and RF blocks, such as regulators, bandgaps, data converters, LNAs, PAs, mixers, and PLLs. Your daily responsibilities include developing RNM models in SystemVerilog with self-checking techniques, creating assertions to ensure analog-digital specifications are met, and collaborating with analog designers to set up AMS simulation environments. You will also debug complex chip digital-on-top testbenches to identify root causes for failures. The role requires strong fundamentals in analog and RF circuit theory, proficiency in SystemVerilog, and experience with Cadence mixed signal verification environments. You must be able to read analog schematics and extract functionality from various components like biasing networks and couplers.