Mixed-Signal Verification Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $129,300–$225,300 / yr
Posted: 143 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k

This role $177k

$117k most similar roles pay here $241k

This role pays less than 58% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $177k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3587 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2768 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Mixed-Signal Verification Engineer

Role Posting Log in to save

The Mixed-Signal Verification Engineer joins the wireless silicon development team to focus on the verification of RF and mixed-signal blocks and their interfaces within a wireless SoC. This role involves reviewing specifications, extracting features, defining execution plans, and developing top or block level testbenches within a UVM framework. The engineer will build and reuse monitors and checkers for RF components while debugging failures, managing bug tracking, and automating flows through scripting. Key technical requirements include expertise in SystemVerilog, Verilog, and the UVM methodology to ensure silicon-correct functionality. Additional preferred skills include experience with real-numbered analog behavioral models, UPF, Python, Matlab, Virtuoso Composer, ADE, and HED. The role addresses critical challenges in wireless SoC design by ensuring optimal coverage and time-to-tapeout trade-offs for high-performance, energy-efficient wireless products.

Skills

System Verilog UVM Verilog Mixed-Signal Verification RF HDL Python Matlab UPF Virtuoso Composer ADE HED

What you'll do

Review specifications and extract features to define and execute verification plans.
Develop top and block level Mixed Signal and Digital testbenches using a UVM framework.
Build and reuse monitors and checkers for RF and Mixed-Signal blocks.
Debug failures, fix testbench or model issues, and manage bug tracking.
Analyze and close coverage to ensure silicon-correct functionality.
Write scripts to automate verification flows.
Improve Mixed Signal verification methodology using novel ideas and AI technologies.

What we're looking for

Bachelor degree in technical disciplines.
2+ years of hands-on experience in Mixed-Signal verification.
Industry experience with RF/Mixed-Signal blocks and SOCs.
Expertise building Mixed-Signal testbenches, checkers, and tests using SystemVerilog.
Experience in UVM methodology and HDL (SystemVerilog, Verilog) for verification.
Understanding of common analog/RF blocks.
Experience with UPF, Python, or Matlab (preferred).
Experience with Virtuoso Composer, ADE, HED, real-numbered behavioral models, or wireless systems (preferred).

Similar roles

Mixed-Signal Verification Engineer

Apple Inc

San Diego, CA 103 days ago $122,700–$214,300

System Verilog UVM Mixed-Signal Verification RF Verilog Python Matlab UPF Virtuoso Composer ADE HED HDL SOC

2+ yrs exp

Save

Mixed-Signal Verification Engineer

Apple Inc

San Francisco, CA 143 days ago $184,700–$324,800

System Verilog UVM Mixed-Signal Verification Verilog HDL Python Matlab UPF Virtuoso Composer ADE HED RF Analog Design Automation Verification Methodology

10+ yrs exp

Save

Mixed-Signal Verification Engineer

Apple Inc

San Diego, CA 143 days ago $175,000–$308,500

System Verilog UVM Mixed-Signal Verification Verilog HDL Python Matlab UPF Virtuoso Composer ADE HED RF Analog Design Verification Methodology

10+ yrs exp

Save

Wireless Radio Verification Engineer

Apple Inc

Sunnyvale, CA 167 days ago $129,300–$225,300

UVM SystemVerilog Python Verilog VHDL Mixed-Signal Verification Assertion-Based Verification RTL Simulation Real-Number Modeling Perl Bash ASIC Verification Digital Design Functional Coverage

Save

Wireless Radio Verification Engineer

Apple Inc

San Diego, CA 167 days ago $122,700–$214,300

UVM SystemVerilog Python Verilog VHDL Mixed-Signal Verification Assertion-Based Verification RTL Simulation Functional Coverage Perl Bash RF Real-Number Modeling ASIC Verification

Save

Mixed Signal Verification Engineer

Apple Inc

Sunnyvale, CA 3 days ago $129,300–$225,300

SystemVerilog RNM AMS Cadence Mixed Signal Verification Analog Design SoC Circuit Theory Data Converters PLLs LNA PA Mixers

3+ yrs exp

Save