Manager, DRAM Product Planning

What you'll do

• Lead technical engagements with customer engineering teams to position Samsung DRAM as the primary choice for next-generation platforms.
• Facilitate collaborative engineering debugging and troubleshooting to resolve complex technical hurdles during evaluation and mass production.
• Analyze customer system architectures to proactively propose optimized, cutting-edge memory solutions.
• Establish a structured co-development framework to sync customer hardware roadmaps with Samsung’s memory technology pipeline.
• Collaborate with customer architects to co-define product specifications, interfaces, and feature sets.
• Design and implement business models focused on Total Cost of Ownership (TCO) reduction and value-added features.
• Manage the entire project execution pipeline from initial design-in and validation through to mass production.
• Identify project risks and execute mitigation strategies to guarantee time-to-market delivery.

What we're looking for

• Bachelor’s degree in Electrical Engineering, Computer Science, or related Physical Science with 10+ years of experience.
• Master’s degree with 8+ years of industry experience.
• PhD with 5+ years of industry experience.
• Strong understanding of DRAM design/architecture, system-level operations (RAS, Memory Controller, memory PHY), and product support.
• Background in SI/PI (Signal/Power Integrity) and timing measurements.
• Familiarity with fab processes, semiconductor manufacturing, and advanced packaging.
• Deep understanding of 2.5D/3D integration (TSV, Micro-bumping, and Hybrid Bonding).
• Proven experience in customer-facing technical roles leading enablement and debugging.
• Experience defining architecture and specifications for next-generation Custom HBM (HBM4+).
• Ability to plan active logic base-dies that integrate core IP (Memory Controller, advanced RAS, and processing elements).
• Proven track record collaborating with foundries and design houses for custom silicon development.
• Experience defining customized interfaces (e.g., Die-to-Die PHY) for bespoke customer architectures.
• Analytical skills to evaluate system-level PPA (Power-Performance-Area) benefits and customer TCO optimization.