Low Power Design Methodology Engineer

Qualcomm

Quick summary

Work type
On-site
Location
San Diego, CA
Salary
$115,600–$173,400 / yr
Posted
5 days ago
Closes
Dec 20, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $144k
$102k most similar roles pay here $241k

This role pays less than 87% of similar roles. Most pay $164,600–$216,250 — the shaded band above. At the midpoint, this role pays about $144k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Qualcomm

Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.

Qualcomm currently has 828 open roles on FindRole.

Listed pay typically runs $148,300–$222,500 across 508 roles with salary data.

Most-posted roles

View all roles at Qualcomm

At a glance

TL;DR · Low Power Design Methodology Engineer

Role Posting Log in to save

Senior Digital ASIC Designer at Qualcomm Technologies, Inc., responsible for designing adaptive power management controllers and digital power meters, performing RTL design and verification tasks, and collaborating with various teams to integrate low-power solutions into wireless SoC chips. The role involves enhancing methodologies across the entire design cycle from RTL to GDS and conducting block-level power analysis. Candidates should have 3 years of experience in low-power digital ASIC design, familiarity with front-end processes including u-arch, RTL coding, simulation, synthesis, and STA, and proficiency in scripting languages like Python, Perl, and TCL. Preferred candidates will also possess expertise in advanced low-power techniques such as UPF and CLP, knowledge of automotive functional safety standards, and strong debugging skills across multiple environments.

Skills

Python Perl TCL Verilog SystemVerilog UPF CLP Make ISO 26262 FMEA FMEDA

What you'll do

  • Design adaptive power management controllers and on-chip sensor controllers.
  • Perform RTL design and formal verification for IP blocks.
  • Integrate low-power solutions into wireless SoC chips.
  • Enable functional safety features in automotive SoC products.
  • Create and enhance low-power methodologies throughout the design cycle.
  • Support block-level and chip-level power analysis.
  • Collaborate with system/software teams to enable low-power features.

What we're looking for

  • 3+ years of experience in low power digital ASIC design.
  • Proficiency in RTL coding, simulation, synthesis, and timing analysis.
  • Familiarity with scripting languages like Python, Perl, and TCL.
  • Understanding of electrical engineering concepts and circuit analysis.
  • Experience with advanced low power techniques such as UPF and CLP.
  • Knowledge of SoC architecture and automotive functional safety standards.
  • Ability to work closely with cross-functional teams on design implementation.

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