This role pays less than
83%
of similar roles. Most pay
$158,862–$220,800
— the shaded band above.
At the midpoint, this role pays about
$144k
versus about
$190k
for comparable roles.
Based on 240 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has
623 open roles
on FindRole.
Listed pay typically runs
$148,300–$222,500
across 603 roles with salary data.
As a Low Power Design/Methodology Engineer within the ASICS Engineering group, you will design adaptive power management controllers, on-chip sensor controllers, and digital power meters. Your daily responsibilities include performing RTL design, simulation, synthesis, timing analysis, lint checks, clock domain crossing checks, and formal verification for IP blocks. You will collaborate with circuit design, physical design, and software teams to integrate low power solutions into wireless and automotive SoC chips while ensuring functional safety features are enabled. The role involves creating and enhancing low power methodologies from RTL to GDS and performing block-level power analysis. Required skills include proficiency in Verilog, SystemVerilog, and scripting languages like Python, Perl, and TCL. You will apply knowledge of UPF, CLP, and AVS while addressing complex power management strategies for the product roadmap.
ASIC
RTL
Verilog
VHDL
System Verilog
UPF
CPF
Conformal Low Power Check
Python
Tcl
Perl
DFT
Synthesis
Timing Closure
Power Analysis
Power Modeling
Prime Power
PowerArtist
PtPx