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Active Keyword: Low Power Design Remove filter Clear all

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Design Engineer (Low Power)

Qualcomm

Santa Clara, CA 73 days ago $176,300–$264,500
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design Low Power Design RTL ARM IP AMBA AHB APB AXI PCIe USB 802.11x Synthesis Timing Closure Emulation Power Intent post silicon bring up
6+ yrs exp
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Low Power Design/Methodology Engineer

Qualcomm

San Diego, CA 81 days ago $115,600–$173,400
Actively hiring Confirmed live yesterday Trusted Below market
ASIC RTL Verilog System Verilog UPF CLP STA Python Tcl Perl Make ISO 26262 FMEA FMEDA Simulation Emulation SoC Architecture
2+ yrs exp
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