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Design Engineer (Low Power)

Qualcomm

Santa Clara, CA 40 days ago $190,200–$285,400
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design Low Power Design RTL Synthesis Timing Closure ARM IP AMBA AHB APB AXI PCIe USB silicon bring up Power Analysis Emulation SoC micro architecture 802.11x Multi-domain Clocking
7+ yrs exp
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