Low Power ASIC Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$100,000–$166,750 / yr
Employment
Full-time
Posted
14 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $184k
This role $133k
$86k $233k
below market most similar roles pay here above market

This role pays less than 84% of similar roles. Most pay $152,875–$214,250 — the blue band above. At the midpoint, this role pays about $133k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Low Power ASIC Engineer

Role Posting Log in to save

JOB TITLE: Low Power ASIC Engineer - New College Grad 2027 The Low Power DV team is seeking a Low Power ASIC Engineer - New College Grad 2027 to support the research and development of energy-efficient GPU and SOC architectures. In this role, you will collaborate with architecture, design, and software teams to architect and develop testbenches, infrastructure, and testplans for verifying power management solutions. You will improve power-aware DV methodologies and influence EDA vendors to enhance simulation and debug efficiencies. Required skills include proficiency in Verilog, SystemVerilog, and UVM, along with experience using Incisive Low-Power, Synopsys VCS NLP, and Verdi. You must understand low power design techniques like multi VT, clock gating, power gating, and DVFS. This work focuses on delivering high perf/watt solutions for AI, Automotive, GeForce, and Mobile products.

Skills

Verilog SystemVerilog UVM Incisive Low-Power Synopsys VCS Verdi Python Perl C C++ UPF DVFS Clock Gating Power Gating Multi VT Makefile

What you'll do

  • Architect and develop testbenches, infrastructure, and testplans to verify power management solutions.
  • Verify various low power design techniques including multi VT, clock gating, and power gating.
  • Implement and verify Dynamic Voltage-Frequency Scaling (DVFS) for GPU and SOC products.
  • Develop power-aware DV methodologies to improve simulation and debug efficiencies.
  • Use Incisive Low-Power or Synopsys VCS NLP to perform hardware verification.
  • Perform hardware debugging using Verdi and other industry-standard tools.
  • Write and maintain simulation programs using Verilog, SystemVerilog, and UVM.
  • Influence EDA vendors to improve simulation and debug performance.

What we're looking for

  • Completed a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or equivalent experience.
  • Understand low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and DVFS.
  • Possess a good understanding of processor architecture (GPU is a plus) and related power management design/DV techniques.
  • Have experience with Incisive Low-Power or Synopsys VCS NLP.
  • Possess strong debug skills and experience with Verdi.
  • Be fluent in Verilog and SystemVerilog with an understanding of UVM.
  • Prior knowledge of Low Power Architecture, Low Power CV, and deep learning (preferred).
  • Good understanding of power intent in UPF format, scripting in Python or PERL, and knowledge of C or C++ (preferred).

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