Integrated Circuit Design Verification Engineer

Snap Inc.

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Hybrid

Quick summary

Work type
Hybrid
Location
—
Salary
$173,000–$259,000 / yr
Posted
95 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $199k
This role $216k
$137k $272k
below market most similar roles pay here above market

This role pays more than 67% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $216k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Snap Inc.

Snap Inc. is a technology and camera company, best known for Snapchat, offering visual communication, augmented reality, and advertising products.

Snap Inc. currently has 94 open roles on FindRole.

Listed pay typically runs $209,000–$313,000 across 84 roles with salary data.

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At a glance

TL;DR · Integrated Circuit Design Verification Engineer

JOB TITLE: Integrated Circuit Design Verification Engineer The Integrated Circuit Design Verification Engineer joins the Spectacles Team to support a multi-disciplinary group designing display Integrated Circuits for AR. The role involves developing and implementing UVM-based and assertion-based testbenches, creating verification test plans, and executing functional and code coverage. The engineer will utilize the Siemens Questa tool set for verification and debug tasks while specifying and configuring tools and creating automation. Key technical requirements include strong knowledge of SystemVerilog, UVM, and Verilog RTL coding practices. Candidates must be proficient in scripting and automation using TCL, Make, Perl, Python, and Shell scripts in a Linux environment. The work focuses on the technical challenges of developing hardware for advanced eyewear that integrates digital experiences into three-dimensional space.

What you'll do

  • Develop and implement UVM-based and assertion-based testbenches for display Integrated Circuits.
  • Create and execute verification test plans including functional and code coverage.
  • Utilize the Siemens Questa tool set for verification and debug tasks.
  • Specify and configure tools and create automation scripts using TCL, Python, and Shell.
  • Perform digital functional simulation and debug tasks for AR hardware.
  • Drive complex verification issues to closure from initial planning through to sign-off.

What we're looking for

  • BSEE, MSEE, or relevant years of experience.
  • Experience in ASIC Design Verification.
  • Strong knowledge of UVM and SystemVerilog for advanced verification methodologies.
  • Strong knowledge of digital functional simulation and Siemens Questa tools.
  • Strong knowledge of Verilog RTL coding practices.
  • Proficiency in scripting and automation using TCL, Make, Perl, Python, and Shell scripts in Linux.
  • Excellent written and verbal English communication skills.
  • Experience with the entire verification process, emulation, RTL design, and various protocols like MIPI and AMBA (preferred).

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