GPU/SOC Low-Power Feature Architect

Nvidia

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CAAustin, TXHillsboro, OR
Salary
$168,000–$264,500 / yr
Employment
Full-time
Posted
28 days ago
Freshness
Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $226k
This role $216k
$155k $291k
below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $196,750–$254,750 — the blue band above. At the midpoint, this role pays about $216k versus about $226k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · GPU/SOC Low-Power Feature Architect

The GPU/SOC Low-Power Feature Architect will join the HW ArchDev team within the Silicon Co-Design Group. This role involves contributing to the design of next-generation high-speed IOs, specifically focusing on NVLink and NVLink-C2C. The architect is responsible for IO power optimizations, pushing energy efficiency, and ensuring interoperability with connected devices in complex interconnect topologies. Daily tasks include deep-diving into technically challenging HSIO bugs and driving debug efforts across various engineering teams. Required skills include experience in capacity-power management, perf/power modeling, and bringup. The candidate must possess strong EE fundamentals, knowledge of computer architecture, timing analysis, process variations, and statistical error rates. This position addresses technical challenges in high-speed interconnect power management and system-level power modeling for active and idle use cases.

What you'll do

  • Design the next generation of high-speed IOs, including NVLink and NVLink-C2C.
  • Perform IO power optimizations to improve overall energy efficiency.
  • Ensure interoperability with connected devices and system components in complex interconnect topologies.
  • Perform deep-dive analysis and lead debug efforts for technically challenging HSIO bugs.
  • Conduct system-level and platform-level power modeling for active and idle use cases.
  • Analyze firmware and driver structures to understand their interactions with hardware.
  • Drive the design, development, and release of next-generation products with cross-functional engineering teams.

What we're looking for

  • BS or MS degree in EE/CE or equivalent experience.
  • Minimum 10 years of experience in capacity, power management, use case analysis, perf/power modeling, bringup, and/or debug.
  • Experience with system-level and interconnect power management optimizations.
  • Experience with silicon and platform-level power modeling for active/idle use cases.
  • Understanding of firmware/driver structures and their interaction with hardware.
  • Track record of influence, leadership, and collaboration across multiple teams.
  • Strong EE fundamentals and knowledge of computer architecture, high-speed interfaces, timing analysis, process variations, and power analysis.

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