below marketmost similar roles pay hereabove market
This role pays less than
79%
of similar roles. Most pay
$177,050–$229,100
— the blue band above.
At the midpoint, this role pays about
$162k
versus about
$203k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3497 open roles
on FindRole.
Listed pay typically runs
$174,149–$277,600
across 2702 roles with salary data.
As a Gate-level SigEM/SEB/FIT CAD Engineer, you will join the CAD Group to assist in developing, maintaining, and refining methodologies and flows for gate-level and transistor-level designs. Your daily responsibilities include supporting the automation, maintenance, and regression testing of CAD flows from setup through sign-off. You will help run, validate, and debug simulation and verification runs on benchmark and production designs while developing verification scripts and rule checks for clock trees and high-speed data paths. The role requires proficiency in Tcl, Python, or Perl scripting and familiarity with commercial EDA tools like Voltus, RedHawk, Primetime, ICC2, Innovus, or SPICE simulators. You will address technical problems involving electromigration, Statistical Electromigration Budgeting, Failure In Time, and thermal analysis for SOC signal and power-grid checks.
Develop, test, and deploy EM, SEB, and thermal analysis methodologies and flows.
Automate, maintain, and perform regression testing on CAD flows from setup through sign-off.
Run, validate, and debug simulation and verification runs on benchmark and production designs.
Develop and maintain verification scripts and rule checks for clock trees and high-speed data paths.
Perform signal EM analysis for clock and data nets and SOC FIT budget verification.
Execute power-grid EM checks and support flow automation tasks.
Triage flow execution issues and gather data for cross-functional teams like Physical Design and Timing.
What we're looking for
BS or MS degree in Electrical Engineering or a related field.
Strong academic foundation in VLSI design, semiconductor physics, circuit theory, or computer engineering (preferred).
Basic understanding of electromigration (EM) mechanisms, heating effects, current density, or chip reliability concepts (preferred).
Exposure to fundamental concepts in static timing analysis (STA), circuit simulation (SPICE), parasitic extraction, or physical design principles (preferred).
Proficiency in at least one of Tcl, Python, or Perl scripting languages (preferred).
Prior internship, co-op, or academic research experience in VLSI design, CAD/EDA flow development, or chip reliability (preferred).
Familiarity or hands-on exposure to commercial EDA tools like Voltus, RedHawk, Primetime, ICC2, Innovus, or SPICE simulators (preferred).
Curiosity about or coursework in AI/ML applications in CAD/EDA workflows (preferred).