Gate-level SigEM/SEB/FIT CAD Engineer

As a Gate-level SigEM/SEB/FIT CAD Engineer within the CAD Group, you will develop, define, and refine methodologies and flows for gate-level and transistor-level designs. Your daily responsibilities include developing comprehensive EM, SEB, and thermal solutions across advanced node designs, managing flow from concept through sign-off, and performing tasks such as IP/SOC signal analysis, FIT budget validation, power-grid verification, and 3DIC thermal integrity. You will collaborate with physical design, circuit, and package teams while working with EDA vendors for tool qualification and model development. Required skills include experience with EM, SEB, FIT, SHE, and thermal calculations, along with proficiency in Tcl, Python, or Perl scripting. You will utilize industry-leading tools like Voltus, Voltus-Fi, RedHawk-SC, and Totem to address reliability challenges in high-performance, large-scale designs and advanced packaging technologies.