Gate-level SigEM/SEB/FIT CAD Engineer

What you'll do

• Define and architect comprehensive EM, SEB, and thermal methodologies for advanced node designs.
• Develop customized EM/SEB/thermal solutions that scale with accuracy and capacity requirements.
• Manage the entire EM/SEB/thermal flow from initial concept through final sign-off and automation.
• Serve as the technical authority on EM/FIT requirements and trade-offs for cross-functional teams.
• Develop and maintain rule decks and verification methodologies for clock trees and high-speed data paths.
• Lead technical engagement with EDA vendors and foundries for tool qualification and model development.
• Conduct correlation studies between analysis tools and silicon failure data to improve methodology.
• Mentor junior engineers on EM, SEB, and thermal analysis techniques and best practices.

What we're looking for

• Minimum of BS degree and 10 years of relevant industry experience.
• Experience with EM, SEB, FIT, SHE, and thermal methodologies and calculations.
• Experience with current density calculations, heating effects, and electromigration failure mechanisms.
• Experience in EDA tools and CAD flow development.
• Proficiency in at least one of Tcl, Python, and/or Perl scripting languages (preferred).
• Experience in at least one analysis involved in EM such as extraction, timing, simulation, modeling, physical design, or verification (preferred).
• Hands-on knowledge of industry leading EMIR tools like Voltus, Voltus-Fi, RedHawk-SC, or Totem (preferred).
• Experience with advanced packaging technologies and AI/ML-driven innovation for CAD workflows (preferred).