Gate-level SigEM/SEB/FIT CAD Engineer

As a Gate-level SigEM/SEB/FIT CAD Engineer, you will join the CAD Group to develop, define, and refine methodologies and flows for gate-level and transistor-level designs. You will be responsible for architecting comprehensive EM, SEB, and thermal solutions across advanced node designs while owning the entire flow from concept through sign-off. Your daily work involves performing IP/SOC signal analysis for clock and data nets, power-grid verification, 3DIC and interposer thermal integrity, and standard cell characterization. You will serve as a technical authority on EM/FIT requirements, engage with EDA vendors for tool qualification, and mentor junior engineers. Required skills include experience in EM, SEB, FIT, SHE, and thermal analysis, along with proficiency in Tcl, Python, or Perl scripting. You will utilize tools like Voltus, Voltus-Fi, RedHawk-SC, and Totem to solve complex reliability issues on high-performance designs.