CAD Gate-level 3DIC EM/IR Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Sunnyvale, CA
Salary
$150,400–$277,600 / yr
Posted
15 days ago
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Confirmed live today

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Competitive pay

How this pay compares to similar roles

Similar $200k
This role $214k
$135k most similar roles pay here $293k

This role pays more than 63% of similar roles. Most pay $168,200–$231,300 — the shaded band above. At the midpoint, this role pays about $214k versus about $200k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

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At a glance

TL;DR · CAD Gate-level 3DIC EM/IR Engineer

As a CAD Gate-level 3DIC EM/IR Engineer, you will join the CAD Group to develop, define, and refine methodologies and flows for gate-level and transistor-level designs. Your daily responsibilities include performing functional static and dynamic IR analysis, scan mode IVD analysis, power EM analysis, SigEM, and power switch modeling. You will also handle package and interposer models, manage 3DIC and multi-die analysis, and perform IP/SoC level EMIR sign-off and ECO. To succeed, you must possess expertise in EDA tools, CAD flows, and EMIR methodologies, alongside proficiency in Tcl, Python, or Perl scripting. You will collaborate with design groups and work with EDA vendors to qualify and debug tools. This role addresses critical power integrity and electromigration challenges within high-performance, large-scale designs and complex multi-die silicon architectures.

What you'll do

  • Develop custom EM/IR solutions that scale with accuracy and capacity challenges.
  • Streamline and automate the entire EM/IR flow.
  • Perform functional static and dynamic IR analysis, including scan mode IVD analysis.
  • Conduct power EM analysis, SigEM, and power switch modeling for 3DIC and multi-die designs.
  • Manage package and interposer model handling for complex integrated circuits.
  • Execute IP and SoC level EM/IR sign-off and ECO processes.
  • Work with EDA vendors and foundries to perform tool qualification, debugging, and enhancement.

What we're looking for

  • Bachelor of Science degree and at least 3 years of relevant industry experience.
  • Experience in EDA tools, CAD flows, and EMIR methodology.
  • Proficiency in Tcl, Python, or Perl scripting languages.
  • Experience in analysis tasks including extraction, timing, noise, simulation, physical design, and/or verification.
  • Ability to coordinate and drive initiatives with little to no oversight (preferred).
  • Excellent communication and presentation skills (preferred).
  • Hands-on knowledge of industry leading EMIR tools such as Voltus, VoltusFi, RedHawk-SC, or Totem (preferred).
  • Experience in large scale software development in multi-user, multi-site environments (preferred).

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