Formal Verification Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Santa Clara, CA
Employment: Full-time
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Similar $184k

$132k $232k

below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $152,875–$216,062.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Formal Verification Engineer

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As a Formal Verification Engineer - New College Grad 2026, you will join the formal verification team to verify RTL units for next generation chip designs. You will own the task of developing comprehensive formal verification testplans, identifying key behaviors for the design under test, and creating verification environments including assumptions, assertions, and cover properties. Your daily work involves applying various formal verification techniques to prove the correctness of digital designs, debugging RTL to identify failure scenarios, and developing scripts to automate the verification process. You must utilize knowledge of CPU and GPU architectures, digital logic, and temporal logic assertions. Required skills include experience with HDLs like Verilog and SystemVerilog, along with formal verification tools such as Jasper, IFV, SMV, and SPIN to solve complex micro-architectural problems.

Skills

Formal Verification System Verilog Verilog RTL Jasper IFV SMV SPIN Temporal Logic Computer Architecture Digital Logic CPU GPU Verification Methodology

What you'll do

Develop comprehensive formal verification testplans and identify key behaviors for the design under test.
Create verification environments including environment assumptions, assertions, and cover properties.
Apply various formal verification techniques to prove the correctness of digital designs.
Debug RTL to identify and resolve specific failure scenarios.
Develop scripts to automate the formal verification process.
Review formal setups and proofs with design and verification teams.

What we're looking for

BS, MS, or Ph.D. in CS, CE, EE, Mathematics, or equivalent experience.
Knowledge and experience in formal verification techniques.
Strong knowledge of CPU/GPU architectures and digital logic.
Hands-on experience with HDLs such as Verilog and System Verilog.
Understanding of temporal logic assertions and abstraction techniques for effective verification.
Ability to understand RTL quickly and strong analytical skills to solve difficult problems.
Excellent communication skills with the ability to collaborate effectively with team members.
Experience with Formal Verification Tools such as Jasper, IFV, SMV, or SPIN (preferred).

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