Formal Verification Engineer

Formal Verification Engineer As part of the Silicon Technologies group, the Formal Verification Engineer will perform complete formal verification for single or multiple design blocks and IPs, including CPU, Cellular, Connectivity, Audio, Image Processing, Neural Networks, Memory/DMA Controllers, Security IP, Interconnects, and Power management subsystems. The role involves collaborating with design engineers to develop micro-architecture specifications, creating comprehensive test plans that include unique security requirements, proving properties of the design, and finding bugs to improve micro-architecture. You will build reusable formal models, architect correct-by-construction methodologies, and model security attacks. Required skills include experience in VLSI, digital logic design, and hardware specifications. Technical competencies include temporal logic assertion-based languages like SVA or PSL, proficiency in scripting languages for debugging, and knowledge of EDA formal tools. The role addresses the technical challenge of ensuring high-quality functional products through robust SoC verification.