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Active Keyword: Digital Design Verification Engineer Remove filter Clear all

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Digital Design Verification Engineer

Broadcom

San Jose, CA +1 18 days ago $101,000–$162,000
Actively hiring Confirmed live today High trust Below market
UVM Design Verification SoC Integration Timing Closure Physical Design Design Debug
5+ yrs exp
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Senior Digital / Mixed-Signal IC Design or Verification Engineer

Broadcom

Mendota Heights, MN +1 24 days ago $109,700–$175,500
Actively hiring Confirmed live yesterday High trust Below market
UVM OVM SystemVerilog Assertions (SVA) Verilog VHDL Python TCL Perl Mixed-Signal Verification Logic Synthesis Static Timing Analysis Formal Verification Place and Route EDA Tools CMOS Bipolar Scripting
8+ yrs exp
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Senior Digital Design Verification Engineer, Hardware

Nvidia

Santa Clara, CA 177 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
SystemVerilog UVM VMM SerDes PCI Express USB SATA Python Perl C/C++ Assertion-based Verification Functional Coverage coverage driven verification Mixed-signal Design Simulation Debug
5+ yrs exp
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