Design Verification

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Cupertino, CA
Salary: $174,149–$225,300 / yr
Posted: 43 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $209k

This role $200k

$138k $262k

below market most similar roles pay here above market

This role pays less than 52% of similar roles. Most pay $177,200–$241,750 — the blue band above. At the midpoint, this role pays about $200k versus about $209k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Design Verification

Role Posting Log in to save

The Design Verification role involves designing and architecting specifications while collaborating closely with design and micro-architecture teams to meet functional and performance goals. The successful candidate will develop test plans, coverage plans, and next generation verification methodologies and test benches. Daily responsibilities include communicating with design, architecture, and software teams to understand use cases and corner conditions to drive specific test cases. The role requires ensuring the quality of the SoC, IP, and subsystems. Technical work involves handling Neural Engine hardware, DRAM subsystems, memory controller logic, Encode and Decode systems for ProRes, VP9, and AV1, hardware security including cryptographic algorithms, high-speed IO standards like PCI Express, DisplayPort, and MIPI, power management, fabric infrastructure, memory cache management, and display subsystems for various products.

Skills

SoC Neural Engine DRAM Subsystems Memory Controller ProRes VP9 AV1 PCI Express DisplayPort MIPI Power Management Fabric Infrastructure Memory Cache Management Display Subsystems Test Plans Verification Methodology

What you'll do

Design and architect specifications for hardware components.
Develop test plans, test cases, and coverage plans for hardware designs.
Define next-generation verification methodologies and test benches.
Communicate with design, architecture, and software teams to identify use cases and corner conditions.
Ensure the quality of SoCs, IPs, and subsystems through rigorous testing.
Implement and verify specific hardware such as Neural Engines, memory controllers, and high-speed IO standards.
Manage verification for power management, fabric infrastructure, and display subsystems.

What we're looking for

Design and architect specifications for hardware components.
Develop test plans, tests, and coverage plans.
Define next-generation verification methodology and test benches.
Collaborate with design, architecture, and software teams to define use cases and corner conditions.
Ensure SoC, IP, and subsystem quality across various hardware types.
Experience with Neural Engine hardware, DRAM subsystems, or memory controller logic.
Experience with Encode/Decode systems, hardware security, or high-speed IO standards (preferred).
Experience with power management, fabric infrastructure, or display subsystems (preferred).

Similar roles

Design Verification Engineer

Apple Inc

Cupertino, CA 57 days ago $155,896–$225,300

System Verilog UVM C C++ Python Perl EDA Tools Digital Design Computer Architecture Constrained Random Verification Functional Coverage ASIC Design Flow High-speed Interface Protocols Regression Analysis Verification IP

3+ yrs exp

Save

Design Verification Engineer

Apple Inc

Austin, TX 44 days ago

SystemVerilog UVM Python Perl C++ C Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture Data Structures Algorithms PCI Express DisplayPort MIPI Hardware Security

3+ yrs exp

Save

Design Verification Engineer

Apple Inc

Cupertino, CA 44 days ago $184,700–$324,800

SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture PCI Express DisplayPort MIPI Data Structures and Algorithms

10+ yrs exp

Save

MAC Design Verification Engineer

Apple Inc

Sunnyvale, CA 2 days ago $129,300–$225,300

SystemVerilog UVM Verilog SystemVerilog Assertion ASIC Verification Python Perl FPGA Palladium Machine Learning AI Bluetooth UWB WLAN Zigbee AMBA DMA MAC PHY

Save

MAC Design Verification Engineer

Apple Inc

San Diego, CA 2 days ago $122,700–$214,300

SystemVerilog UVM Verilog ASIC Verification Python Perl FPGA Palladium SystemVerilog Assertion Constrained Random Testing Functional Coverage Machine Learning Bluetooth UWB WLAN Zigbee AMBA DMA

Save

Design Verification Engineer

Amd

Santa Clara, CA +2 79 days ago $166,400–$249,600

SystemVerilog UVM DDR5 LPDDR5 DFI C/C++ Python Perl RTL Formal Verification GLS NLP XPROP Functional Coverage

8+ yrs exp

Save