Emulation Verification Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: San Francisco, CA
Salary: $184,700–$324,800 / yr
Posted: 50 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $194k

This role $255k

$129k most similar roles pay here $346k

This role pays more than 98% of similar roles. Most pay $168,425–$219,500 — the shaded band above. At the midpoint, this role pays about $255k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

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At a glance

TL;DR · Emulation Verification Engineer

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The Emulation Verification Engineer joins the emulation team to focus on the creation, deployment, and support of advanced emulation environments. This role is central to a chip design effort where the engineer will work to bring up large Wireless SoCs along with mixed signal components on the Palladium platform. Key responsibilities include porting designs onto the platform, developing monitors and checkers, and executing detailed test plans in collaboration with cross-functional teams including Design, Architecture, Power, Silicon Validation, Performance, and Software. The candidate will develop code for design and verification using Verilog, SystemVerilog, and UVM. Required skills include experience with regression management, triaging, and creating test benches from scratch. Preferred technical expertise includes C/C++ DPI, scripting in Perl, Python, or TCL, low power methodologies like UPF, and knowledge of standard emulators such as Veloce or Zebu.

Skills

SystemVerilog Verilog UVM Palladium Emulation Python Perl TCL C++ DPI UPF Regression Management Assertion FPGA Xilinx Altera Veloce Zebu

What you'll do

Bring up large Wireless SoCs and mixed signal components on the emulation platform.
Develop and utilize monitors and checkers specifically for the emulation platform.
Prepare and execute detailed emulation test plans.
Write Verilog, SystemVerilog, and UVM code to support design and verification activities.
Port complex designs onto the Palladium platform.
Perform regression management and triaging of issues.
Integrate mixed signal models into the Palladium platform.

What we're looking for

Bachelor of Science degree and at least 10 years of relevant industry experience.
Experience with SystemVerilog, Verilog, or UVM.
Experience creating test benches from scratch at both the block and system levels.
Experience in regression management and triaging.
Experience with bring up, debugging, and verification in emulation (preferred).
Understanding of tool flow from RTL to Emulation (preferred).
Knowledge of standard emulator flows (Palladium, Veloce, Zebu) or FPGA (Xilinx, Altera) (preferred).
Proven design verification or silicon validation skills (preferred).