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$168,500–$233,050.
Based on 240 similar postings.
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About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3564 open roles
on FindRole.
Listed pay typically runs
$166,600–$277,600
across 2760 roles with salary data.
The Design Verification Engineer joins a wide-ranging group to ensure bug-free first silicon for SoC and IP designs. This role involves all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. You will develop stimulus, checkers, assertions, trackers, and coverage components while performing design bring-up, regression enabling, and debugging test failures. Key responsibilities include tracking progress through various metrics and using LLMs to improve execution efficiency and quality. Required technical skills include SystemVerilog, UVM, and Object-Oriented Programming. You should also possess experience with simulators, waveform viewers, build automation, coverage collection, and gate-level simulations. Knowledge of Python, Perl, or TCL, as well as power-aware UPF methodology, is also expected.
What does a Design Verification Engineer earn?
Median $191200 from 83 postings across 9 companies.
Create detailed test and coverage plans based on the micro-architecture and design specifications.
Develop scalable and portable verification methodologies and environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans for design bring-up and regression enabling.
Debug test failures and fix bugs identified during regression cycles.
Track and report verification progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform verification for RTL freeze and tape-out sign-off.
What we're looking for
BS degree in a technical subject area and a minimum of 3 years of relevant industry experience.
MS degree in a technical subject area and relevant industry experience (preferred).
Strong knowledge of OOP, SystemVerilog, and UVM (preferred).
Strong knowledge in developing scalable and portable testbenches (preferred).
Proven experience with verification methodologies and tools including simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Knowledge of scripting languages such as Python, Perl, or TCL (preferred).
SystemVerilog
UVM
Constrained Random Verification
Digital Simulation
Python
Perl
C++
Assembly
Functional Coverage
Code Coverage
Assertion Methodology
Computer Architecture
Digital Design
PCI Express
DisplayPort
MIPI
Data Structures and Algorithms