below marketmost similar roles pay hereabove market
This role pays more than
54%
of similar roles. Most pay
$168,500–$233,050
— the blue band above.
At the midpoint, this role pays about
$192k
versus about
$201k
for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has
3564 open roles
on FindRole.
Listed pay typically runs
$166,600–$277,600
across 2760 roles with salary data.
JOB TITLE: Design Verification Engineer
As a Design Verification Engineer, you will join a wide-ranging group to enable the production of fully functional first silicon for IP designs. You will be responsible for all phases of pre-silicon verification, including establishing DV methodology, developing test plans based on micro-architecture, and building scalable, portable verification environments. Your daily work involves developing stimulus, checkers, assertions, and trackers while executing design bring-up and debugging test failures. You will use SystemVerilog, UVM, and scripting languages like Python, Perl, or TCL to stress designs and track progress via coverage metrics. Additionally, you will utilize LLMs to improve execution efficiency. This role solves critical hardware problems by ensuring bug-free SoC and IP components through rigorous regression testing, gate-level simulations, and power-aware verification methodologies.
What does a Design Verification Engineer earn?
Median $191200 from 83 postings across 9 companies.
Create detailed test and coverage plans based on the micro-architecture and design specifications.
Develop scalable and portable verification methodologies and environments using SystemVerilog and UVM.
Build verification components including stimulus, checkers, assertions, trackers, and coverage.
Execute verification plans for design bring-up, DV environment bring-up, and regression enabling.
Debug test failures and fix bugs identified during regression testing.
Track and report verification progress using metrics such as bug counts and coverage.
Utilize LLMs and related technologies to improve verification efficiency and quality.
Perform pre-silicon verification to ensure bug-free first silicon for SoC and IP designs.
What we're looking for
BS degree in a technical subject area and a minimum of 3 years of relevant industry experience.
MS degree in a technical subject area (preferred).
Strong knowledge of OOP, SystemVerilog, and UVM (preferred).
Strong knowledge in developing scalable and portable testbenches (preferred).
Proven experience with verification methodologies and tools including simulators, waveform viewers, build/run automation, coverage collection, and gate-level simulations (preferred).
Working experience using LLMs for efficiency and quality (preferred).
Experience with power-aware (UPF) or similar verification methodology (preferred).
Knowledge of scripting languages such as Python, Perl, or TCL (preferred).